PORT A INTERFACE
MOTOROLA
PORT A
4 - 5
(RAMs). The program memory select, data memory select, and X/Y select can be consid-
ered additional address signals, which extend the directly addressable memory from 64K
words to 192K words
total.
Since external logic delay is large relative to RAM timing margins, timing becomes more
difficult as faster DSPs are introduced. The separate read and write strobes used by the
DSP56002 are mutually exclusive, with a guard time between them to avoid an instance
where two data buffers are enabled simultaneously. Other methods using external logic
gates to generate the RAM control inputs require either faster RAM chips or external
data buffers to avoid data bus buffer conflicts.
Figure 4-2 shows an example of external program memory. A typical implementation of
this circuit would use three-byte-wide static memories and would not require any addi-
tional logic. The PS signal is used as the program-memory chip-select signal to enable
the program memory at the appropriate time.
Figure 4-3 shows a similar circuit using the DS signal to enable two data memories and
V
CC
+5 V
16
RD
WR
PS
DS
X/Y
BN
BR
BG
WT
BS
24
V
SS
GROUND
ADDRESS BUS
A0 - A15
DATA BUS
D0 - D23
DSP56002
BUS
CONTROL
OE
R/W
CS
ADDRESS
DATA
PROGRAM MEMORY
24 BIT x N WORDS
Figure 4-2 External Program Space
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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