BUS ARBITRATION AND SHARED MEMORY
4 - 18
PORT A
MOTOROLA
4.7.1
Bus Arbitration Using Only BR and BG With Internal Control
Perhaps the simplest example of a shared memory system using a DSP56002 is shown
in Figure 4-12. The bus arbitration is performed within the DSP#2 by using software.
DSP#2 controls all bus operations by using I/O pin OUT2 to three-state its own port A
and by never accessing port A without first calling the subroutine that arbitrates the bus.
When the DSP#2 needs to use external memory, it uses I/O pin OUT1 to request bus
access and I/O pin IN1 to read bus grant. DSP#1 does not need any extra code for bus
arbitration since the BR and BG hardware handles its bus arbitration automatically. The
protocol for bus arbitration is as follows:
At reset: DSP#2 sets OUT2=0 (BR#2=0) and OUT1=1 (BR#1=1), which gives DSP#1
access to the bus and suspends DSP#2 bus access.
When DSP#2 wants control of the memory, the following steps are performed (see Figure 4-13):
1. DSP# 2 sets OUT1=0 (BR#1=0).
2. DSP# 2 waits for IN1=0 (BG#1=0 and DSP#1 off the bus).
3. DSP#2 sets OUT2=1 (BR#2=1 to let DSP#2 control the bus).
4. DSP#2 accesses the bus for block transfers, etc. at full speed.
5. To release the bus, DSP#2 sets OUT2=0 (BR#2=0) after the last external
access.
6. DSP#2 then sets OUT1=1 (BR#1=1) to return control of the bus to DSP#1.
7. DSP#1 then acknowledges mastership by deasserting BG#1.
4.7.2
Bus Arbitration Using BN, BR, and BG With External Control
Figure 4-14 can be implemented with external bus arbitration logic, which will save pro-
cessing capacity on the DSPs and can make bus access much faster at a cost of addi-
tional hardware. The bus arbitration logic takes control of the external bus by deasserting
an enable signal (E1, E2, and E3) to all DSPs, which will then acknowledge by granting
the bus (BG=0). When a DSP (DSP#1 in Figure 4-14) needs the bus, it will enter the
WAIT state with BN asserted. If DSP#1 has highest priority, the arbitration logic grants
the bus to DSP#1 by asserting E1 (E2 for DSP#2; E3 for DSP#3) to let the DSP know
that it can have the bus. DSP#1 will then deassert BG to tell the arbiter it has taken con-
trol of the bus. When the DSP no longer needs to make an external access it will deas-
sert BN and the arbiter deasserts E1, after which the DSP deasserts BG.
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Freescale Semiconductor, Inc.
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