BUS ARBITRATION AND SHARED MEMORY
4 - 20
PORT A
MOTOROLA
4.7.3
Bus Arbitration Using BR and BG, and WT and BS With No Overhead
By using the circuit shown in Figure 4-15, two DSPs can share memory with hardware
arbitration that requires no software on the part of the DSPs. The protocol for bus arbitra-
tion in Figure 4-15 is as follows:
At RESET assume DSP#1 is not making external accesses so that BR#2 is deasserted.
Hence, BG of DSP#2 is deasserted, which three-states the buffers, giving DSP#2 control
of the memory.
16
SYSTEM MEMORY
32K x 24 X DATA RAM
32K x 24 Y DATA RAM
32K x 24 PROGRAM RAM
ADDRESS
DATA
CONTROL
ADDRESS
DATA
CONTROL
24
5
A
D
C
A
D
C
A
D
C
DSP56002 #1
DSP56002 #2
DSP56002 #3
BG BR BN
BG BR BN
BG BR BN
BUS ARBITRATION LOGIC WITH PRIORITY ENCODER
A1
E1 BR1
A2
E2
BR2
A3
E3 BR3
Figure 4-14 Bus Arbitration Using BN, BR, and BG with External Control
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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