HOST INTERFACE (HI)
5 - 24
PORT B
MOTOROLA
put pin. Also, in the non-DMA mode, the HACK input pin is used for the MC68000 Family
vectored interrupt acknowledge input.
When HM1 or HM0 are set, the DMA mode is enabled, and the HREQ pin is used to
request DMA transfers. When the DMA mode is enabled, the TREQ and RREQ bits select
the direction of DMA transfers. The HACK input pin is used as a DMA transfer acknowl-
edge input. If the DMA direction is from DSP to host, the contents of the selected register
are enabled onto the host data bus when HACK is asserted. If the DMA direction is from
host to DSP, the selected register is written from the host data bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HM0
and HM1. The HI register selected during a DMA transfer is determined by a 2-bit address
counter, which is preloaded with the value in HM1 and HM0. The address counter substi-
tutes for the HA1 and HA0 bits of the HI during a DMA transfer. The host address bit (HA2)
is forced to one during each DMA transfer. The address counter can be initialized with the
INIT bit feature. After each DMA transfer on the host data bus, the address counter is
incremented to the next register. When the address counter reaches the highest register
(RXL or TXL), the address counter is not incremented but is loaded with the value in HM1
and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and elim-
inates the need for the DMA controller to supply the HA2, HA1, and HA0 pins. For 16- or
24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respec-
tively, from the host request rate – i.e., for every two or three host processor data transfers
of one byte each, there is only one 24-bit DSP CPU interrupt.
Hardware, software, individual, and STOP resets clear HM1 and HM0.
5.3.3.2.7
ICR Initialize Bit (INIT) Bit 7
The INIT bit is used by the host processor to force initialization of the HI hardware. Initial-
ization consists of configuring the HI transmit and receive control bits and loading HM1
and HM0 into the internal DMA address counter. Loading HM1 and HM0 into the DMA
address counter causes the HI to begin transferring data on a word boundary rather than
HM1
HM0
Mode
0
0
Interrupt Mode (DMA Off)
0
1
DMA Mode (24 Bit)
1
0
DMA Mode (16 Bit)
1
1
DMA Mode (8 Bit)
Table 5-3 Host Mode Bit Definition
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Freescale Semiconductor, Inc.
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