SERIAL COMMUNICATION INTERFACE (SCI)
6 - 28
PORT C
MOTOROLA
one 24-bit word by “OR”-ing three data bytes read from the three addresses. The following
code fragment requires that R0 initially points to X:$FFF4, register A is initially cleared,
and R3 points to a data buffer. The only programming trick is using BCLR to test bit 1 of
the packing pointer to see if it is pointing to X:$FFF6 and clearing bit 1 to point to X:$FFF4
if it had been pointing to X:$FFF6. This procedure resets the packing pointer after receiv-
ing three bytes.
MOVE
X:(R0),X0
;Copy received data to temporary register
BCLR
#$1,R0
;Test for last byte
;reset pointer if it is the last byte
OR
X0,A
;Pack the data into register A
MOVE
(R0)+
;and increment the packing pointer
JCS
FLAG
;Jump to clean up routine if last byte
RTI
;Else return until next byte is received
FLAG
MOVE
A,(R3)+
;Move the packed data to memory
CLR
A
;Prepare A for packing next three bytes
RTI
;Return until the next byte is received
The length and format of the serial word is defined by the WDS0, WDS1, and WDS2 con-
trol bits in the SCI control register. In the synchronous modes, the start bit, the eight data
bits with LSB first, the address/data indicator bit and/or the parity bit, and the stop bit are
received in that order for SSFTD equals zero (see Figure 6-10 (a)). For SSFTD equals
one, the data bits are transmitted MSB first (see Figure 6-10(b)). The clock source is de-
fined by the receive clock mode (RCM) select bit in the SCR. In the synchronous mode,
the synchronization is provided by gating the clock. In either mode, when a complete word
has been clocked in, the contents of the shift register can be transferred to the SRX and
the flags; RDRF, FE, PE, and OR are changed appropriately. Because the operation of
the SCI receive shift register is transparent to the DSP, the contents of this register are
not directly accessible to the programmer.
6.3.2.4.2
SCI Transmit Registers
The transmit data register is one byte-wide register mapped into four addresses:
X:$FFF3, X:$FFF4, X:$FFF5, and X:$FFF6. In the asynchronous mode, when data is to
be transmitted, X:$FFF4, X:$FFF5, and X:$FFF6 are used, and the register is called STX.
When X:$FFF4 is written, the low byte on the data bus is transferred to the STX; when
X:$FFF5 is written, the middle byte is transferred to the STX; and when X:$FFF6 is writ-
ten, the high byte is transferred to the STX. This structure (see Figure 6-9) makes it easy
for the programmer to unpack the bytes in a 24-bit word for transmission. Location
X:$FFF3 should be written in the 11-bit asynchronous multidrop mode when the data is
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Freescale Semiconductor, Inc.
For More Information On This Product,
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