SERIAL COMMUNICATION INTERFACE (SCI)
MOTOROLA
PORT C
6 - 29
an address and it is desired that the ninth bit (the address bit) be set. When X:$FFF3 is
written, the transmit data register is called STXA, and data from the low byte on the data
bus is stored in STXA. The address data bit will be cleared in the 11-bit asynchronous
multidrop mode when any of X:$FFF4, X:$FFF5, or X:$FFF6 is written. When either STX
or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically,
but not immediately, when the last bit from the previous word has been shifted out – i.e.,
the transmit shift register is empty. Like the receiver, the transmitter is double buffered.
However, there will be a two to four serial clock cycle delay between when the data is
transferred from either STX or STXA to the transmit shift register and when the first bit
appears on the TXD pin. (A serial clock cycle is the time required to transmit one data bit).
23
16 15
8 7
0
X:$FFF6
X:$FFF5
X:$FFF4
STX
STX
STX
MOVE X0, X:$FFF6; TRANSMIT CHARACTER “A”
MOVE X0, X:$FFF5; TRANSMIT CHARACTER “B”
MOVE X0, X:$FFF4; TRANSMIT CHARACTER “C”
NOTE: STX is the same register decoded at three different addresses.
X0
“A”
“B”
“C”
23
16 15
8 7
0
X:$FFF6
X:$FFF5
X:$FFF4
SRX
SRX
SRX
MOVE X0, X:$FFF6; RECEIVE CHARACTER “A”
MOVE X0, X:$FFF5; RECEIVE CHARACTER “B”
MOVE X0, X:$FFF4; RECEIVE CHARACTER “C”
NOTE: SRX is the same register decoded at three different addresses.
X0
“A”
“B”
“C”
(a) Unpacking
(b) Packing
Figure 6-13 Data Packing and Unpacking
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Freescale Semiconductor, Inc.
For More Information On This Product,
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