SYNCHRONOUS SERIAL INTERFACE (SSI)
6 - 80
PORT C
MOTOROLA
6.4.1.2
Serial Receive Data Pin (SRD)
SRD receives serial data and transfers the data to the SSI receive shift register. SRD may
be programmed as a general-purpose I/O pin called PC7 when the SSI SRD function is
not being used. Data is sampled on the negative edge of the bit clock.
6.4.1.3
Serial Clock (SCK)
SCK is a bidirectional pin providing the serial bit rate clock for the SSI interface. The SCK
is a clock input or output used by both the transmitter and receiver in synchronous modes
or by the transmitter in asynchronous modes (see Table 6-6).
Note: Although an external serial clock can be independent of and asynchronous to the
DSP system clock, it must exceed the minimum clock cycle time of 8T (i.e., the sys-
tem clock frequency must be at least four times the external SSI clock frequency).
The SSI needs at least four DSP phases (DSP phase=T) inside each half of the
serial clock.
FLAG0 OUT
(SYNC MODE)
FLAG0 IN
(SYNC MODE)
SC0
SCK
SCD0
SCKD
SYN = 1
SYN = 0
SCD0 = 0
RCLOCK
TCLOCK
INTERNAL BIT CLOCK
SYN = 1
WL1, WL0
WL1, WL0
RX WORD
LENGTH DIVIDER
TX WORD
LENGTH DIVIDER
RX SHIFT REGISTER
TX SHIFT REGISTER
DIVIDE
BY 2
DIVIDE
BY 2
PRESCALE
DIVIDE BY 1
OR
DIVIDE BY 8
DIVIDER
DIVIDE BY 1
TO DIVIDE
BY 256
F
OSC
PSR
PM0 - PM7
RX WORD
CLOCK
TX WORD
CLOCK
SYN = 0
SCD0 = 1
Figure 6-42 SSI Clock Generator Functional Block Diagram
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Freescale Semiconductor, Inc.
For More Information On This Product,
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