DSP56002 OPERATING MODE REGISTER (OMR)
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MEMORY MODULES AND OPERATING MODES
MOTOROLA
3.3.1
Chip Operating Mode (Bits 0 and 1)
The chip operating mode bits, MB and MA, together with MC, define the program mem-
ory maps and the operating mode of the DSP56002. On processor reset, MB and MA are
loaded from the external mode select pins, MODB and MODA, respectively. After the
DSP leaves the reset state, MB and MA can be changed under software control.
3.3.2
Data ROM Enable (Bit 2)
The DE bit enables the two, on-chip, 256X24 data ROMs located between addresses
$0100–$01FF in the X and Y memory spaces. When DE is cleared, the $0100–$01FF
address space is part of the external X and Y data spaces, and the on-chip data ROMs
are disabled. Hardware reset clears the DE bit.
3.3.3
Internal Y Memory Disable Bit (Bit 3)
Bit 3 is defined as Internal Y Memory Disable (YD). When set, all Y Data Memory address-
es are considered to be external, disabling access to internal Y Data Memory. When
cleared, internal Y Data Memory may be accessed according to the state of the DE control
bit. The content of the internal Y Data Memory is not affected by the state of the YD bit.
The YD bit is cleared during hardware reset.
Figure 3-1 DSP56002 Memory Maps shows a graphic representation of the DE and YD
bit effects on the X and Y data memory maps. Table 3-1 also compares the DE and YD
effects on the memory maps.
*
SD
MC YD
DE MB MA
23
8
7
6
5
4
3
2
1
0
*
OPERATING MODES A, B
DATA ROM ENABLE
INTERNAL Y MEMORY DISABLE
OPERATING MODE C
RESERVED
STOP DELAY
RESERVED
RESERVED
*
Figure 3-2 OMR Format
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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