DSP56002 OPERATING MODES
MOTOROLA
MEMORY MODULES AND OPERATING MODES
3 - 7
3.3.4
Chip Operating Mode (Bit 4)
The MC bit, together with bits MA and MB, define the program memory map and the operating
mode of the chip. Upon reset, the processor loads this bit from the MODC external mode se-
lect pin. After the DSP leaves the reset state, MC can be changed under software control.
3.3.5
Reserved (Bit 5)
This bit is reserved for future expansion and will be read as zero during read operations.
3.3.6
Stop Delay (Bit 6)
The SD bit determines the length of the clock stabilization delay that occurs when the
processor leaves the stop processing state. If the stop delay bit is zero when the chip
leaves the stop state, a 64K clock cycle delay is selected before continuing the stop
instruction cycle. However, if the stop delay bit is one, the delay before continuing the
instruction cycle is long enough to allow a clock stabilization period for the internal clock
to begin oscillating and to stabilize. (See the
DSP56002 Technical Data Sheet
(DSP56002/D) for the actual timing values.) When a stable external clock is used, the
shorter delay allows faster start-up of the DSP.
3.3.7
Reserved OMR Bits (Bits 7–23)
These bits are reserved for future expansion and will be read as zero during read operations.
3.4
DSP56002 OPERATING MODES
The user can set the chip operating mode through hardware by pulling high the MODC,
MODB, and MODA pins appropriately, and then assert the RESET pin. When the DSP
leaves the reset state, it samples the mode pins and writes to the OMR to set the initial
operating mode.
Table 3-1 Memory Mode Bits
DE
YD
Data Memory
0
0
Internal ROMs Disabled and their addresses are part of
External Memory
0
1
Internal X Data ROM is Disabled and is part of External
Memory. Internal Y Data RAM and ROM are Disabled and
are part of External Memory
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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