PORT A INTERFACE
4 - 6
PORT A
MOTOROLA
using the X/Y signal to select between them. The three external memory spaces (pro-
gram, X data, and Y data) do not have to reside in separate physical memories; a single
memory can be employed by using the PS, DS, and X/Y signals as additional address
lines to segment the memory into three spaces (see Figure 4-4). Table 4-1 shows how
the PS, DS, and X/Y signals are decoded.
If the DSP is in the development mode, an exception fetch to any interrupt vector location
will cause the X/Y signal to go low when PS is asserted. This procedure is useful for
debugging and for allowing external circuitry to track interrupt servicing.
V
CC
+5 V
16
RD
WR
PS
DS
X/Y
BN
BR
BG
WT
BS
24
V
SS
GROUND
ADDRESS BUS
A0 - A15
DATA BUS
D0 - D23
DSP56002
BUS
CONTROL
DATA
DATA
ADDRESS
ADDRESS
X DATA
MEMORY
24 BITS x N WORDS
Y DATA
MEMORY
24 BITS x N WORDS
OE
R/
W
CS
CE
OE
R/
W
CS
CE
Figure 4-3 External X and Y Data Space
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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