Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
109
2.3.5
Port A Data Direction Register (DDRA)
2.3.6
Port B Data Direction Register (DDRB)
Table 2-5. PORTB Register Field Descriptions
Field
Description
7-0
PB
Port B general purpose input/output data
—Data Register
Port B pins 7 through 0 are associated with address outputs ADDR[7:0] respectively in expanded modes. In
emulation modes the address is multiplexed with IVD[7:0]. In normal expanded mode pin 0 is related to the UDS
input.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Address 0x0002 (PRR)
Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
7
6
5
4
3
2
1
0
R
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-3. Port A Data Direction Register (DDRA)
Table 2-6. DDRA Register Field Descriptions
Field
Description
7-0
DDRA
Port A Data Direction
—
This register controls the data direction of pins 7 through 0.
The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits
will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Address 0x0003 (PRR)
Access: User read/write
(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
7
6
5
4
3
2
1
0
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-4. Port B Data Direction Register (DDRB)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
