MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
1140
29.1
Introduction
The FTM1024K5 module implements the following:
•
1024 Kbytes of P-Flash (Program Flash) memory, consisting of 5 physical Flash blocks, intended
primarily for nonvolatile code storage
•
32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
•
4 Kbytes of buffer RAM, consisting of 1 physical RAM block, that can be used as emulated
EEPROM using a built-in hardware scheme, as basic RAM, or as a combination of both
The Flash memory is ideal for single-supply applications allowing for field reprogramming without
requiring external high voltage sources for program or erase operations. The Flash module includes a
memory controller that executes commands to modify Flash memory contents or configure module
resources for emulated EEPROM operation. The user interface to the memory controller consists of the
indexed Flash Common Command Object (FCCOB) register which is written to with the command, global
address, data, and any required command parameters. The memory controller must complete the execution
of a command before the FCCOB register can be written to with a new command.
CAUTION
A Flash word or phrase must be in the erased state before being
programmed. Cumulative programming of bits within a Flash word or
phrase is not allowed.
The RAM and Flash memory may be read as bytes, aligned words, or misaligned words. Read access time
is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. For Flash memory,
an erased bit reads 1 and a programmed bit reads 0.
It is not possible to read from a Flash block while any command is executing on that specific Flash block.
It is possible to read from a Flash block while a command is executing on a different Flash block.
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve
single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that
programming be done on an aligned 8 byte basis (a Flash phrase).
29.1.1
Glossary
Buffer RAM
— The buffer RAM constitutes the volatile memory store required for EEE. Memory space
in the buffer RAM not required for EEE can be partitioned to provide volatile memory space for
applications.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
