Appendix C PCB Layout Guidelines
MC9S12XE-Family Reference Manual , Rev. 1.19
1262
Freescale Semiconductor
Appendix C
PCB Layout Guidelines
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
•
Central point of the ground star should be the VSS3 pin.
•
Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
•
VSSPLL must be directly connected to VSS3.
•
Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C7,
C8, and Q1 as small as possible.
•
Do not place other signals or supplies underneath area occupied by C7, C8, and Q1 and the
connection area to the MCU.
•
Central power input should be fed in at the VDDA/VSSA pins.
Example layouts are illustrated on the following pages.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
