Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
138
Freescale Semiconductor
2.3.46
Port P Input Register (PTIP)
3
PTP
Port P general purpose input/output data
—Data Register
Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1
.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2
PTP
Port P general purpose input/output data
—Data Register
Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1
.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
1
PTP
Port P general purpose input/output data
—Data Register
Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1
.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
0
PTP
Port P general purpose input/output data
—Data Register
Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1
.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Address 0x0259
Access: User read
(1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-44. Port P Input Register (PTIP)
Table 2-41. PTP Register Field Descriptions (continued)
Field
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
