Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
144
Freescale Semiconductor
2.3.54
Port H Input Register (PTIH)
2.3.55
Port H Data Direction Register (DDRH)
1
PTH
Port H general purpose input/output data
—Data Register
Port H pin 1 is associated with the TXD signal of the SCI6 module and the MOSI signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTH
Port H general purpose input/output data
—Data Register
Port H pin 0 is associated with the RXD signal of the SCI6 module and the MISO signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Address 0x0261
Access: User read
(1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-52. Port H Input Register (PTIH)
Table 2-50. PTIH Register Field Descriptions
Field
Description
7-0
PTIH
Port H input data
—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Address 0x0262
Access: User read/write
(1)
7
6
5
4
3
2
1
0
R
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-53. Port H Data Direction Register (DDRH)
Table 2-49. PTH Register Field Descriptions (continued)
Field
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
