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Freescale Semiconductor HCS12X, Reference Manual

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Chapter 2 Port Integration Module (S12XEP100PIMV1)

MC9S12XE-Family Reference Manual , Rev. 1.19

Freescale Semiconductor

145

1. Read: Anytime.

Write: Anytime.

Table 2-51. DDRH Register Field Descriptions

Field

Description

7

DDRH

Port H data direction

—

This register controls the data direction of pin 7.
The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

6

DDRH

Port H data direction

—

This register controls the data direction of pin 6.
The enabled SCI5 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

5

DDRH

Port H data direction

—

This register controls the data direction of pin 5.
The enabled SCI4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

4

DDRH

Port H data direction

—

This register controls the data direction of pin 4.
The enabled SCI4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

3

DDRH

Port H data direction

—

This register controls the data direction of pin 3.
The enabled SCI7 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

2

DDRH

Port H data direction

—

This register controls the data direction of pin 2.
The enabled SCI7 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.

Because 

of 

an 

order 

from 

the 

United 

States 

International 

Trade 

Commission, 

BGA-packaged 

product 

lines 

and 

part 

numbers 

indicated 

here 

currently 

are 

not 

available 

from 

Freescale 

for 

import 

or 

sale 

in 

the 

United 

States 

prior 

to 

September 

2010: 

S12XE 

products 

in 

208 

MAPBGA 

packages

Summary of Contents for HCS12X

Page 1: ...00RMV1 Rev 1 19 12 2008 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale...

Page 2: ...Added further 384K derivative Updated DBG section Jan 2008 1 15 Added further s12XES384 derivative Updated FTM DBG SCI sections May 2008 1 16 Figure B 3 1 value corrected Added LVR minimum assert leve...

Page 3: ...ced Capture Timer ECT16B8CV3 525 Chapter 15 Inter Integrated Circuit IICV3 577 Chapter 16 Scalable Controller Area Network S12MSCANV3 603 Chapter 17 Periodic Interrupt Timer S12PIT24B8CV2 659 Chapter...

Page 4: ...rical Characteristics 1201 Appendix B Package Information 1257 Appendix C PCB Layout Guidelines 1262 Appendix D Derivative Differences 1267 Appendix E Detailed Register Address Map 1270 Appendix F Ord...

Page 5: ...Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in t...

Page 6: ...Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in t...

Page 7: ...4 System States 79 1 5 Security 80 1 6 Resets and Interrupts 80 1 6 1 Resets 80 1 6 2 Vectors 80 1 6 3 Effects of Reset 84 1 7 ADC0 Configuration 86 1 7 1 External Trigger Input Connection 86 1 7 2 AD...

Page 8: ...Register PTT 121 2 3 22 Port T Input Register PTIT 122 2 3 23 Port T Data Direction Register DDRT 122 2 3 24 Port T Reduced Drive Register RDRT 123 2 3 25 Port T Pull Device Enable Register PERT 123 2...

Page 9: ...egister PPSJ 153 2 3 67 Port J Interrupt Enable Register PIEJ 154 2 3 68 Port J Interrupt Flag Register PIFJ 154 2 3 69 Port AD0 Data Register 0 PT0AD0 155 2 3 70 Port AD0 Data Register 1 PT1AD0 155 2...

Page 10: ...176 2 3 106Port F Polarity Select Register PPSF 177 2 3 107PIM Reserved Register 177 2 3 108Port F Routing Register PTFRR 177 2 4 Functional Description 178 2 4 1 General 178 2 4 2 Registers 178 2 4...

Page 11: ...roduction 241 5 1 1 Glossary or Terms 242 5 1 2 Features 242 5 1 3 Modes of Operation 242 5 1 4 Block Diagram 243 5 2 External Signal Description 243 5 3 Memory Map and Register Definition 245 5 3 1 M...

Page 12: ...bug Module S12XBDMV2 7 1 Introduction 277 7 1 1 Features 277 7 1 2 Modes of Operation 278 7 1 3 Block Diagram 279 7 2 External Signal Description 279 7 3 Memory Map and Register Definition 280 7 3 1 M...

Page 13: ...kpoints 340 Chapter 9 Security S12XE9SECV2 9 1 Introduction 345 9 1 1 Features 345 9 1 2 Modes of Operation 346 9 1 3 Securing the Microcontroller 346 9 1 4 Operation of the Secured Microcontroller 34...

Page 14: ...Information 461 10 9 1 Initialization 461 10 9 2 Code Example Transmit Hello World on SCI 461 10 9 3 Stack Support 464 Chapter 11 S12XE Clocks and Reset Generator S12XECRGV1 11 1 Introduction 467 11 1...

Page 15: ...on 502 13 1 3 Block Diagram 503 13 2 Signal Description 504 13 2 1 Detailed Signal Descriptions 504 13 3 Memory Map and Register Definition 504 13 3 1 Module Memory Map 504 13 3 2 Register Description...

Page 16: ...m 578 15 2 External Signal Description 578 15 2 1 IIC_SCL Serial Clock Line Pin 578 15 2 2 IIC_SDA Serial Data Line Pin 578 15 3 Memory Map and Register Definition 579 15 3 1 Register Descriptions 579...

Page 17: ...PIT24B8CV2 17 1 Introduction 659 17 1 1 Glossary 659 17 1 2 Features 659 17 1 3 Modes of Operation 659 17 1 4 Block Diagram 660 17 2 External Signal Description 660 17 3 Register Definition 661 17 4 F...

Page 18: ...Channel 4 693 19 2 5 PWM3 PWM Channel 3 693 19 2 6 PWM3 PWM Channel 2 693 19 2 7 PWM3 PWM Channel 1 693 19 2 8 PWM3 PWM Channel 0 693 19 3 Memory Map and Register Definition 693 19 3 1 Module Memory...

Page 19: ...Interface S12SPIV5 21 1 Introduction 761 21 1 1 Glossary of Terms 761 21 1 2 Features 761 21 1 3 Modes of Operation 761 21 1 4 Block Diagram 762 21 2 External Signal Description 763 21 2 1 MOSI Maste...

Page 20: ...22 4 1 Prescaler 809 22 4 2 Input Capture 810 22 4 3 Output Compare 810 22 4 4 Pulse Accumulator 811 22 4 5 Event Counter Mode 811 22 4 6 Gated Time Accumulation Mode 811 22 5 Resets 812 22 6 Interru...

Page 21: ...troduction 831 24 1 1 Glossary 832 24 1 2 Features 833 24 1 3 Block Diagram 834 24 2 External Signal Description 835 24 3 Memory Map and Registers 836 24 3 1 Module Memory Map 836 24 3 2 Register Desc...

Page 22: ...ossary 954 26 1 2 Features 955 26 1 3 Block Diagram 956 26 2 External Signal Description 957 26 3 Memory Map and Registers 958 26 3 1 Module Memory Map 958 26 3 2 Register Descriptions 963 26 4 Functi...

Page 23: ...1 Glossary 1078 28 1 2 Features 1079 28 1 3 Block Diagram 1080 28 2 External Signal Description 1081 28 3 Memory Map and Registers 1082 28 3 1 Module Memory Map 1082 28 3 2 Register Descriptions 1087...

Page 24: ...Supply 1201 A 1 3 Pins 1202 A 1 4 Current Injection 1203 A 1 5 Absolute Maximum Ratings 1203 A 1 6 ESD Protection and Latch up Immunity 1204 A 1 7 Operating Conditions 1206 A 1 8 Power Dissipation an...

Page 25: ...age 1260 B 4 80 Pin QFP Package 1261 Appendix C PCB Layout Guidelines Appendix D Derivative Differences D 1 Memory Sizes and Package Options S12XE Family 1267 D 2 Pinout explanations 1269 Appendix E D...

Page 26: ...use of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the Un...

Page 27: ...new enhanced version has improved interrupt handling capability and is fully compatible with the existing XGATE module The MC9S12XE Family is composed of standard on chip peripherals including up to 6...

Page 28: ...trace buffer captures change of flow or memory access information BDM background debug mode MPU memory protection unit 8 address regions definable per active program task Address range granularity as...

Page 29: ...r erase and word program operation Ability to program up to four words in a burst sequence Emulated EEPROM Features Automatic EEE file handling using an internal Memory Controller Automatic transfer o...

Page 30: ...annel x 8 bit or 4 channel x 16 bit Pulse Width Modulator programmable period and duty cycle per channel Center or left aligned outputs Programmable clock select logic with a wide range of frequencies...

Page 31: ...z maximum CPU bus frequency 100MHz maximum XGATE bus frequency 1 1 2 Modes of Operation Memory map and bus interface modes Normal and emulation operating modes Normal single chip mode Normal expanded...

Page 32: ...llator COP Watchdog IPLL with Frequency Modulation option Debug Module 4 address breakpoints 2 data breakpoints 512 Byte Trace Buffer Reset Generation and Test Entry RXD TXD SCI1 Asynchronous Serial I...

Page 33: ...annel 48 0x00B0 0x00B7 IIC1 inter IC bus 8 0x00B8 0x00BF SCI2 serial communications interface 8 0x00C0 0x00C7 SCI3 serial communications interface 8 0x00C8 0x00CF SCI0 serial communications interface...

Page 34: ...2C0 0x02EF ATD0 analog to digital converter 12 bit 16 channel 48 0x02F0 0x02F7 Voltage regulator 8 0x02F8 0x02FF Reserved 8 0x0300 0x0327 PWM pulse width modulator 8 channels 40 0x0328 0x032F Reserved...

Page 35: ...M window 1K EEPROM 2K REGISTERS 1K EEPROM window 16K FLASH Unpaged 16K FLASH 2K REGISTERS Unimplemented RAM External Space RAM_LOW FLASH FLASH_LOW Unimplemented FLASH RESOURCES NOTE On smaller derivat...

Page 36: ...le as a 9S12XEQ512 die thus the unimplemented FLASH pages are those of the 9S12XEQ512 device map The 9S12XEG128 is currently only available as a 9S12XET256 die thus the unimplemented FLASH pages are t...

Page 37: ...13_F000 4 32 9S12XEx384 0x78_00005 5The 384K memory map is split into a 128K block from 0x78_0000 to 0x79_FFFF and a 256K block from 0x7C_0000 to 0x7F_FFFF 24 0x0F_A000 6 0x13_F000 4 32 9S12XET256 9S1...

Page 38: ...block The block B0 is a reduced size 64K block on the 128K derivative 9S12XEG128 9S12XEA1281 B1S 64K B0 64K 1The 9S12XEA devices are special bondouts for access to extra ADC channels in 80QFP Availabl...

Page 39: ...x0800 Registers 0x00_07FF XGATE Local Memory Map Global Memory Map FLASHSIZE XGRAMSIZE RAMSIZE 0x78_0800 FLASH RAM XGRAM_LOW XGFLASH_HIGH Because of an order from the United States International Trade...

Page 40: ...PARTIDH and PARTIDL addresses 0x001A and 0x001B The read only value is a unique part ID for each revision of the chip Table 1 6 shows the assigned part ID number and Mask Set number Because of an ord...

Page 41: ...urrently available as MC9S12XEP100 die only 4M48H 0xCC94 0xFFFF MC9S12XEP7682 5M48H 0xCC94 0x0004 MC9S12XEQ512 0M25J 0xC480 0xFFFF MC9S12XEQ512 1M25J 0xC481 0xFFFF MC9S12XEQ512 2M25J 0xC482 0xFFFF MC9...

Page 42: ...ted modules Refer to Appendix D Derivative Differences for more information about derivative device module subset and to Table 1 7 Port Availability by Package Option and Table 1 9 Pin Out Summary for...

Page 43: ...AD11 H PR3 PR4 PT4 VDDF VSSX VSSX VSSX VSSX VSSA PAD26 PAD03 PAD10 J PT5 PR5 PT6 VSS1 VSSX VSSX VSSX VSSX VSS2 PAD09 PAD25 PAD02 K PR6 PT7 PK4 PR7 VSSX VSSX VSSX VSSX VDD PD7 PAD24 PAD01 L PK5 PJ1 BKG...

Page 44: ...6 ADDR14 PA5 ADDR13 PA4 ADDR12 PA3 ADDR11 PA2 ADDR10 PA1 ADDR9 PA0 ADDR8 PP4 KWP4 PWM4 MISO2 TIMIOC4 PP5 KPW5 PWM5 MOSI2 TIMIOC5 PP6 KWP6 PWM6 SS2 TIMIOC6 PP7 KWP7 PWM7 SCK2 TIMIOC7 PK7 ROMCTL EWAIT V...

Page 45: ...PK2 PK1 PK0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDDF VSS1 IOC4 PT4 VREGAPI IOC5 PT5 IOC6 PT6 IOC7 PT7 PK5 PK4 TXD2 KWJ1 PJ1 RXD2 KWJ0 PJ0 MODC BKGD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 TXD5 SS2 KWH7 PH7 R...

Page 46: ...RXCAN0 PJ7 KWJ7 TXCAN4 SCL0 TXCAN0 TEST PS3 TXD1 PS2 RXD1 PS1 TXD0 PS0 RXD0 VSSA1 VRL TIMIOC3 SS1 PWM3 KWP3 PP3 TIMIOC2 SCK1 PWM2 KWP2 PP2 TIMIOC1 MOSI1 PWM1 KWP1 PP1 TIMIOC0 MISO1 PWM0 KWP0 PP0 IOC0...

Page 47: ...RXCAN1 RXCAN0 MISO0 PM3 TXCAN1 TXCAN0 SS0 PM4 RXCAN2 RXCAN0 RXCAN4 MOSI0 PM5 TXCAN2 TXCAN0 TXCAN4 SCK0 PJ6 KWJ6 RXCAN4 SDA0 RXCAN0 PJ7 KWJ7 TXCAN4 SCL0 TXCAN0 TEST PS3 TXD1 PS2 RXD1 PS1 TXD0 PS0 RXD0...

Page 48: ...g of pin functions is summarized in Table 1 8 Table 1 9 provides a pin out summary listing the availability of individual pins for each package option Because of an order from the United States Intern...

Page 49: ...amily members Port AD ADC Channels 32 32 24 24 16 16 8 8 12 12 Port A pins 8 8 8 8 4 Port B pins 8 8 8 8 8 Port C pins 8 8 0 0 0 Port D pins 8 8 0 0 0 Port E pins inc IRQ XIRQ input only 8 8 8 8 8 Por...

Page 50: ...7 6 X PH 1 0 O X PH 3 2 O X PH 5 4 O X PH 7 6 O X PJ 0 O O PJ 1 O PJ 2 O PJ 3 PJ 4 O O PJ 5 O O PJ 7 6 X O O PL 1 0 X PL 3 2 X PL 5 4 X PL 7 6 X PM 1 0 O PM 3 2 X O X PM 5 4 X O X X PM 7 6 O X O PP 3...

Page 51: ...ADDR22 ACC2 E2 7 5 PK3 ADDR19 IQSTAT3 E3 8 6 PK2 ADDR18 IQSTAT2 D1 9 7 PK1 ADDR17 IQSTAT1 E1 10 8 PK0 ADDR16 IQSTAT0 VDDX VDDX7 VSSX VSSX7 F3 11 9 5 PT0 IOC0 F2 PR0 TIMIOC0 G4 12 10 6 PT1 IOC1 F1 PR1...

Page 52: ...PC1 DATA9 N1 30 PC2 DATA10 N2 31 PC3 DATA11 P1 32 24 16 PB0 ADDR0 IVD0 UDS M3 33 25 17 PB1 ADDR1 IVD1 N3 34 26 18 PB2 ADDR2 IVD2 P2 35 27 19 PB3 ADDR3 IVD3 P3 36 28 20 PB4 ADDR4 IVD4 R2 37 29 21 PB5...

Page 53: ...SSX 52 40 28 VSSX2 VDDX 53 41 29 VDDX2 P8 54 42 30 RESET N8 55 43 31 VDDR N9 56 44 32 VSS3 R9 T8 57 45 33 VSSPLL T9 58 46 34 EXTAL T10 59 47 35 XTAL R10 T11 60 48 36 VDDPLL P9 PL7 TXD7 N10 61 49 PH3 K...

Page 54: ...10 IVD10 P15 76 60 44 PA3 ADDR11 IVD11 P16 77 61 45 PA4 ADDR12 IVD12 N15 78 62 46 PA5 ADDR13 IVD13 M13 79 63 47 PA6 ADDR14 IVD14 N16 80 64 48 PA7 ADDR15 IVD15 VSSX 81 VSSX3 VDDX 82 VDDX3 L14 83 PD4 DA...

Page 55: ...E16 PAD28 AN28 F14 99 77 56 PAD05 AN05 F15 100 78 PAD13 AN13 D16 PAD29 AN29 E15 101 79 57 PAD06 AN06 C16 102 80 PAD14 AN14 D15 PAD30 AN30 C15 103 81 58 PAD07 AN07 E14 104 82 PAD15 AN15 B15 PAD31 AN31...

Page 56: ...X VSSX6 VDDX VDDX6 B10 123 93 PS4 MISO0 A11 124 94 PS5 MOSI0 A10 125 95 PS6 SCK0 C9 126 96 PS7 SS0 B9 127 97 67 TEST D9 128 98 68 PJ7 KWJ7 TXCAN4 SCL0 TXCAN0 A9 129 99 69 PJ6 KWJ6 RXCAN4 SDA0 RXCAN0 C...

Page 57: ...40 108 PK7 ROMCTL EWAIT A3 141 109 78 PP7 KWP7 PWM7 SCK2 TIMIOC7 B3 142 110 PP6 KWP6 PWM6 SS2 TIMIOC6 C4 143 111 79 PP5 KWP5 PWM5 MOSI2 TIMIOC5 C3 144 112 80 PP4 KWP4 PWM4 MISO2 TIMIOC4 1 Standard 80Q...

Page 58: ...data bus PD 7 0 DATA 7 0 VDDX PUCR Disabled Port D I O data bus PE7 ECLKX2 XCLKS VDDX PUCR Up Port E I O system clock output clock select PE6 TAGHI MODB VDDX While RESET pin is low down Port E I O tag...

Page 59: ...CAN4 SCL0 TXCAN0 VDDX PERJ PPSJ Up Port J I O interrupt TX of CAN4 SCL of IIC0 TX of CAN0 PJ6 KWJ6 RXCAN4 SDA0 RXCAN0 VDDX PERJ PPSJ Up Port J I O interrupt RX of CAN4 SDA of IIC0 RX of CAN0 PJ5 KWJ5...

Page 60: ...RXCAN4 MOSI0 VDDX PERM PPSM Disabled Port M I O CAN0 CAN2 CAN4 MOSI of SPI0 PM3 TXCAN1 TXCAN0 SS0 VDDX PERM PPSM Disabled Port M I O TX of CAN1 CAN0 SS of SPI0 PM2 RXCAN1 RXCAN0 MISO0 VDDX PERM PPSM D...

Page 61: ...of SPI0 PS5 MOSI0 VDDX PERS PPSS Up Port S I O MOSI of SPI0 PS4 MISO0 VDDX PERS PPSS Up Port S I O MISO of SPI0 PS3 TXD1 VDDX PERS PPSS Up Port S I O TXD of SCI1 PS2 RXD1 VDDX PERS PPSS Up Port S I O...

Page 62: ...up state As an output it is driven low to indicate when any internal MCU reset source triggers The RESET pin has an internal pull up device 1 2 3 3 TEST Test Pin This input only pin is reserved for t...

Page 63: ...5 0 V The input voltage thresholds for PC 7 0 are configured to reduced levels out of reset in expanded and emulation modes The input voltage thresholds for PC 7 0 are configured to 5 V levels out of...

Page 64: ...shold for PE5 is configured to reduced levels out of reset in expanded and emulation modes 1 2 3 15 PE4 ECLK Port E I O Pin 4 PE4 is a general purpose input or output pin It can be configured to drive...

Page 65: ...XD5 Port H I O Pin 7 PH7 is a general purpose input or output pin It can be configured as a keypad wakeup input It can be configured as slave select pin SS of the serial peripheral interface 2 SPI2 It...

Page 66: ...uring master mode or slave input pin during slave mode MOSI of the serial peripheral interface 1 SPI1 It can also be configured as the transmit pin TXD of serial communication interface 6 SCI6 1 2 3 3...

Page 67: ...configured as a keypad wakeup input It can be configured as the receive pin RXD of the serial communication interface 2 SCI2 It can also be configured as chip select output 3 1 2 3 41 PK7 EWAIT ROMCTL...

Page 68: ...L I O Pin 4 PL4 is a general purpose input or output pin It can be configured as the receive pin RXD of serial communication interface 6 SCI6 1 2 3 48 PL3 TXD5 Port L I O Pin 3 PL3 is a general purpo...

Page 69: ...4 It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the serial peripheral interface 0 SPI0 1 2 3 56 PM3 TXCAN1 TXCAN0 SS0 Port M I O Pin 3 PM3...

Page 70: ...figured as pulse width modulator PWM channel 4 output TIM channel 4 or as the master input during master mode or slave output during slave mode pin MISO of the serial peripheral interface 2 SPI2 1 2 3...

Page 71: ...5 MOSI0 Port S I O Pin 5 PS5 is a general purpose input or output pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the serial peripheral interf...

Page 72: ...ands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible NOTE All VSS pins must be connected together in the application 1 2 4...

Page 73: ...the supply voltage to the oscillator and PLL to be bypassed independently This voltage is generated by the internal voltage regulator No static external loading of these pins is permitted Table 1 11...

Page 74: ...pendently Internal power and ground generated by internal regulator VSSPLL 0 V Table 1 11 Power and Ground Connection Summary continued Mnemonic Nominal Voltage Description Because of an order from th...

Page 75: ...e on chip phase locked loop PLL the PLL self clocking the oscillator The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock As shown in Figure...

Page 76: ...when full system performance is not required These are described in 1 4 2 Power Modes Some modules feature a software programmable option to freeze the module status whilst the background debug module...

Page 77: ...er reset in this mode 1 4 1 4 Emulation of Expanded Mode Developers use this mode for emulation systems in which the users target application is normal expanded mode Code is executed from external mem...

Page 78: ...stem Stop is exited on an XGATE request then as long as the XGATE does not set an interrupt flag on the CPU and the XGATE fake activity bit FACT remains cleared once XGATE activity is completed System...

Page 79: ...avior of the ATD0 ATD1 ECT PWM and PIT when the background debug module is active consult the corresponding Block Guides 1 4 4 System States To facilitate system integrity the MCU can run in Superviso...

Page 80: ...n processing 1 6 1 Resets Resets are explained in detail in the Clock Reset Generator CRG description Table 1 13 Reset Sources and Vector Locations 1 6 2 Vectors Table 1 14 lists all interrupt sources...

Page 81: ...E 6F Enhanced capture timer overflow I bit TSRC2 TOF No Yes Vector base DC 6E Pulse accumulator A overflow I bit PACTL PAOVI No Yes Vector base DA 6D Pulse accumulator input edge I bit PACTL PAI No Ye...

Page 82: ...A2 51 CAN2 receive I bit CAN2RIER RXFIE No Yes Vector base A0 50 CAN2 transmit I bit CAN2TIER TXEIE 2 0 No Yes Vector base 9E 4F CAN3 wake up I bit CAN3RIER WUPIE Yes Yes Vector base 9C 4E CAN3 errors...

Page 83: ...gger 3 I bit XGMCTL XGIE No Yes Vector base 6A 35 XGATE software trigger 4 I bit XGMCTL XGIE No Yes Vector base 68 34 XGATE software trigger 5 I bit XGMCTL XGIE No Yes Vector base 66 33 XGATE software...

Page 84: ...n the FTM FSTAT register becoming set If the CPU accesses any EEE RAM location before Vector base 4C 26 TIM timer channel 4 I bit TIE C4I No Yes Vector base 4A 25 TIM timer channel 5 I bit TIE C5I No...

Page 85: ...reset 1 6 3 6 COP Configuration The COP timeout rate bits CR 2 0 and the WCOP bit in the COPCTL register are loaded on rising edge of RESET from the Flash register FOPT See Table 1 15 and Table 1 16...

Page 86: ...ADC module includes four external trigger inputs ETRIG0 ETRIG1 ETRIG2 and ETRIG3 The external trigger feature allows the user to synchronize ADC conversion to external trigger events Table 1 18 shows...

Page 87: ...he VREG high temperature trimming register bits VREGHTTR 3 0 are loaded from the internal Flash during the reset sequence To use the high temperature interrupt within the specified limits THTIA and TH...

Page 88: ...de or full stop mode The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above described reset cases Figure 1 10 Loop Controlled Pierce Oscillator Con...

Page 89: ...terrupt source Port H associated with 4 SCI modules inputs can be used as an external interrupt source Port J associated with 1 MSCAN 1 SCI 2 IIC modules and chip select outputs inputs can be used as...

Page 90: ...gisters to enable disable reduced output drive on Ports T S M P H J AD0 AD1 R L and F on per pin basis Single control register to enable disable reduced output drive on Ports A B C D E and K on per po...

Page 91: ...output multiplexed with IVIS data Mode dependent 4 GPIO I O General purpose I O B PB 7 1 ADDR 7 1 mux IVD 7 1 3 O Low order external bus address output multiplexed with IVIS data Mode dependent 4 GPI...

Page 92: ...write output for external bus WE O Write enable signal GPIO I O General purpose I O PE 1 IRQ I Maskable level or falling edge sensitive interrupt input GPI I General purpose input PE 0 XIRQ I Non mas...

Page 93: ...PS5 MOSI0 I O Serial Peripheral Interface 0 master out slave in pin GPIO I O General purpose I O PS4 MISO0 I O Serial Peripheral Interface 0 master in slave out pin GPIO I O General purpose I O PS3 T...

Page 94: ...l Interface 0 master out slave in pin If CAN0 is routed to PM 3 2 the SPI0 can still be used in bidirectional master mode GPIO I O General purpose I O PM3 TXCAN1 O MSCAN1 transmit pin TXCAN0 O MSCAN0...

Page 95: ...ulse Width Modulator output channel 3 SS1 I O Serial Peripheral Interface 1 slave select output in master mode input for slave mode or master mode TIMIOC3 I O Timer Channel 3 input output GPIO KWP3 I...

Page 96: ...al Peripheral Interface 1 slave select output in master mode input for slave mode or master mode TXD7 O Serial Communication Interface 7 transmit pin GPIO KWH3 I O General purpose I O with interrupt P...

Page 97: ...rpose I O with interrupt PJ2 CS1 O Chip select 1 GPIO KWJ2 I O General purpose I O with interrupt PJ1 TXD2 O Serial Communication Interface 2 transmit pin GPIO KWJ1 I O General purpose I O with interr...

Page 98: ...ose I O F PF7 TXD3 O Serial Communication Interface 3 transmit pin GPIO GPIO I O General purpose I O PF6 RXD3 I Serial Communication Interface 3 receive pin GPIO I O General purpose I O PF5 SCL0 O Int...

Page 99: ...DDRC R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W 0x0007 DDRD R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 W 0x0008 PORTE R PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 W 0x0009 DDRE R DDRE7 DDRE6 DDR...

Page 100: ...DRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 W 0x0034 0x023F Non PIM Address Range R Non PIM Address Range W 0x0240 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PT...

Page 101: ...DRS0 W 0x024C PERS R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0...

Page 102: ...RP R RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 W 0x025C PERP R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R PIE...

Page 103: ...026B RDRJ R RDRJ7 RDRJ6 RDRJ5 RDRJ4 RDRJ3 RDRJ2 RDRJ1 RDRJ0 W 0x026C PERJ R PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 W 0x026D PPSJ R PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W 0x026E PIE...

Page 104: ...1AD14 PT1AD13 PT1AD12 PT1AD11 PT1AD10 W 0x027A DDR0AD1 R DDR0AD17 DDR0AD16 DDR0AD15 DDR0AD14 DDR0AD13 DDR0AD12 DDR0AD11 DDR0AD10 W 0x027B DDR1AD1 R DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD1...

Page 105: ...L7 PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0 W 0x0371 PTIL R PTIL7 PTIL6 PTIL5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 W 0x0372 DDRL R DDRL7 DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0 W 0x0373 RDRL R RDRL7 RDRL6 RDRL5...

Page 106: ...PTF3 PTF2 PTF1 PTF0 W 0x0379 PTIF R PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0 W 0x037A DDRF R DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 W 0x037B RDRF R RDRF7 RDRF6 RDRF5 RDRF4 RDRF3 RDRF2...

Page 107: ...Input Pull Up Falling edge 0 x x 1 1 1 Input Pull Down Rising edge 1 0 0 x x 0 Output full drive to 0 Disabled Disabled 1 1 0 x x 0 Output full drive to 1 Disabled Disabled 1 0 1 x x 0 Output reduced...

Page 108: ...expanded modes In emulation modes the address is multiplexed with IVD 15 8 When not used with the alternative function these pins can be used as general purpose I O If the associated data direction bi...

Page 109: ...DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W Reset 0 0 0 0 0 0 0 0 Figure 2 3 Port A Data Direction Register DDRA Table 2 6 DDRA Register Field Descriptions Field Description 7 0 DDRA Port A Data Direction This re...

Page 110: ...n the data direction value Write Anytime In emulation modes write operations will also be directed to the external bus 7 6 5 4 3 2 1 0 R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 W Altern Function DATA15 DATA14...

Page 111: ...ated with data I O lines DATA 7 0 respectively in expanded modes When not used with the alternative function these pins can be used as general purpose I O If the associated data direction bits of thes...

Page 112: ...he data direction value Write Anytime In emulation modes write operations will also be directed to the external bus 7 6 5 4 3 2 1 0 R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 W Reset 0 0 0 0 0...

Page 113: ...associated with external bus control signals and interrupt inputs These include mode select MODB MODA E clock double frequency E clock Instruction Tagging High and Low TAGHI TAGLO Read Write RW Read...

Page 114: ...ssociated pins In this case the data direction bits will not change When operating a pin as a general purpose I O the associated data direction bit determines whether it is an input or output 1 Associ...

Page 115: ...ll Port D input pins This bit configures whether pull up devices are activated if the pins are used as inputs This bit has no effect if the pins are used as outputs Out of reset the pull up devices ar...

Page 116: ...f all Port K output pins as either full or reduced If a pin is used as input this bit has no effect 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled 6 5 Res...

Page 117: ...Read Anytime In emulation modes read operations will return the data from the external bus in all other modes the data source is depending on the data direction value Write Anytime In emulation modes...

Page 118: ...DIV16 Free running ECLK predivider Divide by 16 This bit enables a divide by 16 stage on the selected EDIV rate 1 Divider enabled ECLK rate EDIV rate divided by 16 0 Divider disabled ECLK rate EDIV r...

Page 119: ...ed to respond only to falling edges Falling edges on the IRQ pin will be detected anytime IRQE 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt 0 IRQ configured for low le...

Page 120: ...22 16 Access Source ACC 2 0 External Wait EWAIT and instruction pipe signals IQSTAT 3 0 Bits 6 0 carry the external addresses in all expanded modes In emulation modes the address is multiplexed with...

Page 121: ...pins can be used as general purpose I O If the associated data direction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read 5 PTT...

Page 122: ...1 0 R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W Reset 0 0 0 0 0 0 0 0 Figure 2 21 Port T Data Direction Register DDRT Table 2 22 DDRT Register Field Descriptions Field Description 7 0 DDRT Por...

Page 123: ...uced If a pin is used as input this bit has no effect 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x0244 Access User read write 1 1 Read Anytim...

Page 124: ...ull down device is connected to the associated pin if enabled and if the pin is used as input 0 A pull up device is connected to the associated pin if enabled and if the pin is used as input Address 0...

Page 125: ...can be used as general purpose I O If the associated data direction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read 4 PTS Port...

Page 126: ...red pin input state is read Address 0x0249 Access User read 1 1 Read Anytime Write Never writes to this register have no effect 7 6 5 4 3 2 1 0 R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W Rese...

Page 127: ...e channel is enabled The data direction bits revert to controlling the I O direction of a pin when the associated channel is disabled 1 Associated pin is configured as output 0 Associated pin is confi...

Page 128: ...ll device enabled 0 Pull device disabled Address 0x024D Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W Reset 0 0 0 0 0 0 0 0...

Page 129: ...he output is driven active low only open drain A logic level of 1 is not driven This allows a multipoint connection of several serial modules These bits have no influence on pins used as inputs 1 Outp...

Page 130: ...f the associated data direction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read 5 PTM Port M general purpose input output data...

Page 131: ...n be used as general purpose I O If the associated data direction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read 2 PTM Port M...

Page 132: ...sociated pin is configured as output 0 Associated pin is configured as input 6 DDRM Port M data direction This register controls the data direction of pin 6 The enabled CAN3 routed CAN4 or routed SCI3...

Page 133: ...data direction of pin 2 The enabled CAN1 or routed CAN0 forces the I O state to be an input Depending on the configuration of the enabled routed SPI0 this pin will be forced to be input or output In...

Page 134: ...full drive strength 0 Full drive strength enabled Address 0x0254 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 W Reset 0 0 0 0...

Page 135: ...up device is connected to the associated Port M pin if enabled by the associated bit in register PERM and if the port is used as general purpose or RXCAN input Address 0x0256 Access User read write 1...

Page 136: ...ODRR Related Pins 6 5 4 3 2 1 0 RXCAN TXCAN CAN0 x x x x x 0 0 PM0 PM1 x x x x x 0 1 PM2 PM3 x x x x x 1 0 PM4 PM5 x x x x x 1 1 PJ6 PJ7 CAN4 x x x 0 0 x x PJ6 PJ7 x x x 0 1 x x PM4 PM5 x x x 1 0 x x...

Page 137: ...ions these pins can be used as general purpose I O If the associated data direction bits of these pins are set to 1 a read returns the value of the port register otherwise the buffered pin input state...

Page 138: ...of SPI1 The PWM function takes precedence over the SPI1 and the general purpose I O function if the PWM channel 1 is enabled The SPI1 function takes precedence of the general purpose I O function if t...

Page 139: ...Register DDRP Table 2 43 DDRP Register Field Descriptions Field Description 7 DDRP Port P data direction This register controls the data direction of pin 7 The enabled PWM channel 7 forces the I O sta...

Page 140: ...1 5 of the full drive strength 0 Full drive strength enabled Address 0x025C Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Re...

Page 141: ...enabled by the associated bit in register PERP and if the port is used as input 0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register A pull up device is conn...

Page 142: ...PPSP register To clear this flag write logic level 1 to the corresponding bit in the PIFP register Writing a 0 has no effect 1 Active edge on the associated bit has occurred an interrupt will occur i...

Page 143: ...ter otherwise the buffered pin input state is read 4 PTH Port H general purpose input output data Data Register Port H pin 4 is associated with the RXD signal of the SCI4 module and the MISO signal of...

Page 144: ...nce over the general purpose I O function if the SCI6 is enabled When not used with the alternative function this pin can be used as general purpose I O If the associated data direction bit of this pi...

Page 145: ...in is configured as output 0 Associated pin is configured as input 4 DDRH Port H data direction This register controls the data direction of pin 4 The enabled SCI4 forces the I O state to be an input...

Page 146: ...is pin will be forced to be input or output In those cases the data direction bits will not change The DDRM bits revert to controlling the I O direction of a pin when the associated peripheral module...

Page 147: ...W Reset 0 0 0 0 0 0 0 0 Figure 2 56 Port H Polarity Select Register PPSH Table 2 54 PPSH Register Field Descriptions Field Description 7 0 PPSH Port H pull device select Determine pull device polarit...

Page 148: ...d write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 W Reset 0 0 0 0 0 0 0 0 Figure 2 58 Port H Interrupt Flag Register PIFH Table 2 56 PPSP Registe...

Page 149: ...ort J general purpose input output data Data Register This pin is associated with the SCL and SDA signals of IIC1 and with chip select outputs CS2 and CS0 respectivley The IIC1 function takes preceden...

Page 150: ...ction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read Address 0x0269 Access User read 1 1 Read Anytime Write Never writes to th...

Page 151: ...utput In those cases the data direction bits will not change The DDRM bits revert to controlling the I O direction of a pin when the associated peripheral module is disabled 1 Associated pin is config...

Page 152: ...ontrolling the I O direction of a pin when the associated peripheral module is disabled 1 Associated pin is configured as output 0 Associated pin is configured as input Address 0x026B Access User read...

Page 153: ...0 W Reset 0 0 0 0 0 0 0 0 Figure 2 64 Port J Polarity Select Register PPSJ Table 2 62 PPSJ Register Field Descriptions Field Description 7 0 PPSJ Port J pull device select Determine pull device polari...

Page 154: ...d write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W Reset 0 0 0 0 0 0 0 0 Figure 2 66 Port J Interrupt Flag Register PIFJ Table 2 64 PPSP Registe...

Page 155: ...e port register otherwise the buffered pin input state is read Address 0x0271 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT...

Page 156: ...DDR0AD01 DDR0AD00 W Reset 0 0 0 0 0 0 0 0 Figure 2 69 Port AD0 Data Direction Register 0 DDR0AD0 Table 2 67 DDR0AD0 Register Field Descriptions Field Description 7 0 DDR0AD0 Port AD0 data direction T...

Page 157: ...put Address 0x0274 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00 W Reset 0 0 0 0 0 0 0 0 Figure 2 71 P...

Page 158: ...selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x0276 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PER0AD07 PER0AD06 PER0AD05 PER0AD04...

Page 159: ...led Address 0x0278 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PT0AD17 PT0AD16 PT0AD15 PT0AD14 PT0AD13 PT0AD12 PT0AD11 PT0AD10 W Altern Function AN15 AN14 AN13 AN12 AN11 AN...

Page 160: ...be used as general purpose I O If the associated data direction bits of these pins are set to 1 a read returns the value of the port register otherwise the buffered pin input state is read Address 0x...

Page 161: ...nput function on Port AD1 the ATD Digital Input Enable Register ATD1DIEN1 has to be set to logic level 1 Address 0x027B Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R DDR1AD17...

Page 162: ...d approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x027D Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R RDR1AD17 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD1...

Page 163: ...no pull device is enabled 1 Pull device enabled 0 Pull device disabled Address 0x027F Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PER1AD17 PER1AD16 PER1AD15 PER1AD14 PER1AD...

Page 164: ...he associated data direction bit of this pin is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read Address 0x0369 Access User read 1 1 Read Anytime W...

Page 165: ...ugh 0 The TIM forces the I O state to be an output for each timer port associated with an enabled output compare In this case the data direction bits will not change The data direction bits revert to...

Page 166: ...0 0 0 0 0 0 0 Figure 2 87 Port R Pull Device Enable Register PERR Table 2 85 PERR Register Field Descriptions Field Description 7 0 PERR Port R pull device enable Enable pull devices on input pins The...

Page 167: ...nimplemented or Reserved Figure 2 89 PIM Reserved Register Address 0x036F Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PTRRR7 PTRRR6 PTRRR5 PTRRR4 PTRRR3 PTRRR2 PTRRR1 PTRRR...

Page 168: ...TIMIOC2 is available on PR2 1 PTRRR Port R routing This register configures the re routing of the associated TIM channel 1 TIMIOC1 is available on PP1 0 TIMIOC1 is available on PR1 0 PTRRR Port R rout...

Page 169: ...ster otherwise the buffered pin input state is read 3 PTL Port L general purpose input output data Data Register Port L pin 3 is associated with the TXD signal of the SC5 module When not used with the...

Page 170: ...0 0 Figure 2 93 Port L Data Direction Register DDRL Table 2 90 DDRL Register Field Descriptions Field Description 7 0 DDRL Port L data direction This register controls the data direction of pins 7 th...

Page 171: ...ed If a pin is used as input this bit has no effect 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x0374 Access User read write 1 1 Read Anytime...

Page 172: ...enabled and if the pin is used as input Address 0x0376 Access User read write 1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R WOML7 WOML6 WOML5 WOML4 WOML3 WOML2 WOML1 WOML0 W Reset 0 0 0 0 0 0 0 0 F...

Page 173: ...Summary Module PTLRR Related Pins 7 6 5 4 TXD RXD SCI7 0 x x x PH3 PH2 1 x x x PL7 PL6 SCI6 x 0 x x PH1 PH0 x 1 x x PL5 PL4 SCI5 x x 0 x PH7 PH6 x x 1 x PL3 PL2 SCI4 x x x 0 PH5 PH4 x x x 1 PL1 PL0 A...

Page 174: ...ster otherwise the buffered pin input state is read 3 PTF Port F general purpose input output data Data Register Port F pin 3 is associated with the TXD signal of the SC5 module When not used with the...

Page 175: ...0 0 0 Figure 2 101 Port F Data Direction Register DDRF Table 2 98 DDRF Register Field Descriptions Field Description 7 0 DDRF Port F data direction This register controls the data direction of pins 7...

Page 176: ...ced If a pin is used as input this bit has no effect 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x037C Access User read write 1 1 Read Anytime...

Page 177: ...device is connected to the associated pin if enabled and if the pin is used as input 0 A pull up device is connected to the associated pin if enabled and if the pin is used as input Address 0x037E Acc...

Page 178: ...3 All registers can be written at any time however a specific configuration might not become active Example 2 1 Selecting a pull up device This device does not become active while the port is used as...

Page 179: ...an input or an output If a peripheral module controls the pin the contents of the data direction register is ignored Figure 2 107 Table 2 103 Register availability per port 1 1 Each cell represents on...

Page 180: ...ly active if the pin is used as an input A pull up device can be activated if the pin is used as a wired or output 2 4 2 7 Wired or mode register WOMx If the pin is used as an output this register tur...

Page 181: ...ADDR15 ADDR8 and ADDR7 ADDR0 respectively PB0 is the ADDR0 or UDS output 2 4 3 3 Port C D Port C pins PC 7 0 and Port D pins PD 7 0 can be used for either general purpose I O with the external bus int...

Page 182: ...n be enabled by clearing the X bit in the CPU condition code register It is inhibited at reset so this pin is initially configured as a high impedance input with a pull up Port E pins PE 5 and PE 6 ar...

Page 183: ...rpose I O or with the SPI1 subsystem 2 4 3 10 Port H This port is associated with the SPI1 SPI2 and SCI7 4 Port H pins PH 7 4 can be used for either general purpose I O or with the SPI2 subsystem Port...

Page 184: ...or with the channels of the standard Timer The TIM channels can be re routed 2 4 3 15 Port L This port is associated with SCI7 4 Port L pins PL 7 6 can be used for either general purpose I O or with...

Page 185: ...s Figure 2 109 shorter than a specified time from generating an interrupt The minimum time varies over process conditions temperature and voltage Figure 2 108 and Table 2 104 Figure 2 108 Interrupt Gl...

Page 186: ...ollowing condition is true on any pin individually Sample count 4 and interrupt enabled PIE 1 and interrupt flag not set PIF 0 2 5 Initialization Information 2 5 1 Port Data and Data Direction Registe...

Page 187: ...olled in this module The local address space for each master is translated to a global memory space Table 3 1 Revision History Revision Number Revision Date Sections Affected Description of Changes V0...

Page 188: ...ormal Single Chip Mode Special Single Chip Mode emulation modes Emulation Single Chip Mode Emulation Expanded Mode normal modes Normal Single Chip Mode Normal Expanded Mode special modes Special Singl...

Page 189: ...store instructions a CPU or BDM 64 KByte local map defined using specific resource page RPAGE EPAGE and PPAGE registers and the default instruction set The 64 KBytes visible at any instant can be cons...

Page 190: ...e user is advised to refer to the device overview for port configuration and location of external bus signals Some pins may not be bonded out in all implementations Table 3 3 and Table 3 4 outline the...

Page 191: ...after RESET active low ROMCTL I ROM control input Latched after RESET active low Table 3 4 External Output Signals Associated with the MMC Signal I O Description Available in Modes NS SS NX ES EX ST C...

Page 192: ...GP4 GP3 GP2 GP1 GP0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reserved R 0 0 0 0 0 0 0 0 W 0x0013 MMCCTL1 R TGMRAMON 0 EEEIFRON PGMIFRON RAMHM EROMON ROMHM ROMON W 0x0014 Reserv...

Page 193: ...during an CPU access which makes use of this register could lead to unexpected results Address 0x000A PRR 7 6 5 4 3 2 1 0 R CS3E1 CS3E0 CS2E1 CS2E0 CS1E1 CS1E0 CS0E1 CS0E0 W Reset 0 0 0 0 0 0 0 ROMON1...

Page 194: ...l address range is shown in Table 3 7 and Figure 3 17 Chip select 1 is only active if enabled in Normal Expanded mode Emulation Expanded mode The function disabled in all other operating modes 00 Chip...

Page 195: ...3 4 Write restrictions exist to disallow transitions between certain modes Figure 3 5 illustrates all allowed mode changes Attempting non authorized transitions will not change the MODE bits but it wi...

Page 196: ...1 0 0 101 RESET SS 110 111 000 RESET RESET RESET RESET RESET 010 101 011 001 100 EX NX NS ES ST RESET Transition done by external pins MODC MODB MODA Transition done by write access to the MODE regist...

Page 197: ...3 1 This example demonstrates usage of the GPAGE register LDX 0x5000 Set GPAGE offset to the value of 0x5000 MOVB 0x14 GPAGE Initialize GPAGE register with the value of 0x14 GLDAA X Load Accu A from...

Page 198: ...Direct Addressing Mode MOVB 0x80 DIRECT Set DIRECT register to 0x80 Write once only Global data accesses to the range 0xXX_80XX can be direct Logical data accesses to the range 0x80XX are direct LDY 0...

Page 199: ...t is used to made the EEE Tag RAM nd FTM SCRATCH RAM visible in the global memory map 0 Not visible in the memory map 1 Visible in the memory map 5 EEEIFRON EEE IFR visible in the memory map Write Any...

Page 200: ...and anytime in special modes This bit is used in some modes to define the placement of the ROM Refer to Table 3 12 0 Disables the Flash or ROM from the memory map 1 Enables the Flash or ROM in the me...

Page 201: ...ead to unexpected results Figure 3 12 PPAGE Address Mapping NOTE Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the instruction ex...

Page 202: ...er is effectively used to construct paged RAM addresses in the Local map format CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpect...

Page 203: ...M in the Global map within the 64 KByte Local map The EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map format CAUTION XGATE write access to this regi...

Page 204: ...external accesses are allowed Special single chip mode This mode is generally used for debugging single chip operation boot strapping or security related operations The active background debug mode i...

Page 205: ...ry Map Scheme 3 4 2 1 CPU and BDM Memory Map Scheme The BDM firmware lookup tables and BDM register memory locations share addresses with other modules however they are not visible in the memory map d...

Page 206: ...1K EEPROM window 16K FLASH Unpaged 16K FLASH 2K REGISTERS 2K RAM 253 4K paged RAM 1K EEPROM 255 1K paged EEPROM 253 16K paged FLASH 16K FLASH PPAGE 0xFD 8K RAM External Space 16K FLASH PPAGE 0xFE 16K...

Page 207: ...rupt vectors point to locations in this area or to the other unpaged sections of the local CPU memory map Table 3 16 summarizes mapping of the address bus in Flash External space based on the address...

Page 208: ...GPAGE register 22 16 see Figure 3 7 BDM Global Addresses Based on the Global Page The seven BDMGPR Global Page index bits allow access to the full 8 Mbyte address map that can be accessed with 23 add...

Page 209: ...bal addresses which are not occupied by the on chip resources unimplemented areas or external memory space result in accesses to the external bus see Figure 3 19 Table 3 17 Global Implemented Memory S...

Page 210: ...misaligned word access from the BDM module will occur these accesses are blocked in the BDM module Refer to BDM Block Guide Misaligned word access to the last location of RAM is performed but the dat...

Page 211: ...F Reset Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x0C00 0x2000 0x0800 8K RAM 4K RAM window 1K EEPROM 2K REGISTERS 1K EEPROM window 16K FLASH Unpaged 16K FLASH 2K REGISTERS U...

Page 212: ...access is always translated to the global address 0x78_0800 0x78_7FFF Example 3 3 is a general example of the XGATE memory map implementation Example 3 3 The MCU FLASHSIZE is 64 Kbytes 0x10000 and MCU...

Page 213: ...0x00_07FF XGATE Local Memory Map Global Memory Map FLASHSIZE XGRAMSIZE RAMSIZE 0x78_0800 FLASH RAM XGRAM_LOW 0x78_7FFF 0x7FFF XGRAMSIZE Unimplemented area Because of an order from the United States I...

Page 214: ...dicated global address Table 3 19 ROMHM and RAMHM Address Location Local Address ROMHM RAMHM Global Address Location 0x4000 0x7FFF 0 X 0x7F_4000 0x7F_7FFF Internal Flash 1 0 0x14_4000 0x14_7FFF Extern...

Page 215: ...2K RAM 251 4K paged RAM 1K EEPROM 255 1K paged EEPROM 253 16K paged FLASH 16K FLASH 16K FLASH PPAGE 0xFE 16K FLASH PPAGE 0xFF 0x00_1000 0x0F_C000 0x13_FC00 0x40_0000 0x7F_4000 0x7F_8000 0x7F_C000 1M m...

Page 216: ...and denoted by RAMSIZE Figure 3 22 S12XE System RAM in the Memory Map 0x7F_FFFF 0x00_0000 0x13_FFFF 0x0F_FFFF EEPROM Area 0x00_07FF 0x3F_FFFF RAM Area in the Memory Map FLASH Area RAMSIZE REG Area Ext...

Page 217: ...Flash in any modes in case of load store access XGATE performs an access to a secured Flash in expanded modes in case of load store or opcode or vector fetch accesses For further details refer to the...

Page 218: ...talled after finishing the current operation and the BDM will gain access to the bus In emulation modes all internal accesses are visible on the external bus as well and the external bus is used durin...

Page 219: ...are stored Using indirect addressing for both the new page value and the address within the page allows usage of values calculated at run time rather than immediate values that must be known at the t...

Page 220: ...to the emulated registers external access located in the PRU in the emulator All read operations are performed from external registers external access in emulation modes In all other modes the read o...

Page 221: ...fetches are internal see Figure 3 24 Table 3 21 PRR Listing PRR Name PRR Local Address PRR Location PORTA 0x0000 PIM PORTB 0x0001 PIM DDRA 0x0002 PIM DDRB 0x0003 PIM PORTC 0x0004 PIM PORTD 0x0005 PIM...

Page 222: ...s see Figure 3 25 Figure 3 25 ROM in Emulation Single Chip Mode 3 5 3 3 ROM Control in Normal Expanded Mode In normal expanded mode the external bus will be connected to the application If the ROMON b...

Page 223: ...ode ROMON 1 Application MCU ROMON 0 Application MCU Flash Memory Memory Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated...

Page 224: ...the data and traces all CPU actions see Figure 3 27 When the ROMON bit is cleared the application memory provides the data and the emulator will observe the CPU internal actions see Figure 3 28 Figur...

Page 225: ...SH provides the data otherwise the application memory provides the data see Figure 3 29 Figure 3 29 ROM in Special Test Mode Application MCU Memory Emulator Observer Application MCU Memory ROMON 0 App...

Page 226: ...ale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for im...

Page 227: ...d into multiple address range comparators The output of the comparators is used to determine if a particular Table 4 1 Revision History Revision Number Revision Date Sections Affected Description of C...

Page 228: ...protection descriptors each descriptor can cover the full global memory map 8 MBytes each descriptor has a granularity of 8 Bytes 1 Master 3 can be implemented or left out depending the chip configur...

Page 229: ...to memory not covered by any protection descriptor will cause an access violation 4 1 4 Modes of Operation The MPU module can be used in all MCU modes 4 2 External Signal Description The MPU module ha...

Page 230: ...0 0 0 SEL 2 0 W 0x0006 MPUDESC0 1 1 The module addresses 0x0006 0x000B represent a window in the register map through which different descriptor registers are visible R MSTR0 MSTR1 MSTR2 MSTR3 LOW_ADD...

Page 231: ...ng this This is to prevent the case that the CPU cannot clear the AEF bit if the registers are write protected for the CPU in supervisor state Note This bit should only be cleared by an access from th...

Page 232: ...ontain bits 22 16 of the global address which caused the current access violation interrupt These bits are undefined if the access error flag bit AEF in the MPUFLG register is not set Address Module B...

Page 233: ...0 0 0 0 Field Description 7 SVSEN MPU supervisor state enable bit This bit enables the memory protection for the CPU in supervisor state If this bit is cleared the MPU does not affect any accesses co...

Page 234: ...is implemented on the device 0 0 0 0 Field Description 7 MSTR0 Master 0 select bit If this bit is set the descriptor is valid for bus master 0 CPU in supervisor state 6 MSTR1 Master 1 select bit If t...

Page 235: ...ess Module Base 0x0008 7 6 5 4 3 2 1 0 R LOW_ADDR 10 3 W Reset 0 0 0 0 0 0 0 0 Field Description 7 0 LOW_ADDR 10 3 Memory range lower boundary address bits The LOW_ADDR 10 3 bits represent bits 10 3 o...

Page 236: ...sed as the upper boundary for the described memory range Address Module Base 0x000A 7 6 5 4 3 2 1 0 R HIGH_ADDR 18 11 W Reset 1 1 1 1 1 1 1 1 Field Description 7 0 HIGH_ADDR 18 11 Memory range upper b...

Page 237: ...CPU accesses are masked from the MPU module as well 4 4 1 Protection Descriptors Each of the eight protection descriptors can be used to restrict the allowed types of memory accesses for a given memo...

Page 238: ...ned only while the AEF bit is set The CPU in supervisor state can read from and write to the peripheral register space even if there is no memory protection descriptor explicitly allowing this This is...

Page 239: ...vice routine with RTI Instead the interrupt request will be asserted again only when the next illegal S12X CPU access is detected 4 5 Initialization Application Information 4 5 1 Initialization After...

Page 240: ...ale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for im...

Page 241: ...ange with external memory peripherals or PRU and provide visibility to the internal bus externally in combination with an emulator Table 5 1 Revision History Revision Number Revision Date Sections Aff...

Page 242: ...k System Clock Refer to CRG Block Guide expanded modes Normal Expanded Mode Emulation Single Chip Mode Emulation Expanded Mode Special Test Mode single chip modes Normal Single Chip Mode Special Singl...

Page 243: ...d signals are described in other sections ECLK ECLKX2 free running clocks PIM section TAGHI TAGLO tag inputs PIM section S12X_DBG section Table 5 2 outlines the pin names and gives a brief description...

Page 244: ...No No Yes Yes Yes Yes IVD 15 1 O Internal visibility read data No No No Yes Yes Yes ADDR0 O T F External address No No No Yes Yes Yes IVD0 O Internal visibility read data No No No Yes Yes Yes UDS O U...

Page 245: ...current operating mode allows user control Please refer the individual bit descriptions 5 3 2 1 External Bus Interface Control Register 0 EBICTL0 Read Anytime In emulation modes read operations will...

Page 246: ...the unused data pins and the data select signals UDS and LDS are free to be used for alternative functions 0 DATA 15 8 UDS and LDS disabled 1 DATA 15 8 UDS and LDS enabled 4 0 ASIZ 4 0 External Addres...

Page 247: ...age is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses to the related address range If configured respectively stretch cycles are added as programmed or dependent on EWAIT i...

Page 248: ...address space as shown in Table 5 8 Table 5 8 External Access Stretch Bit Definition EXSTRx 2 0 Number of Stretch Cycles 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Table 5 9 Summary of Functions...

Page 249: ...es Bus signals ADDR 22 1 DATA 15 0 ADDR 22 20 ACC 2 0 ADDR 19 16 IQSTAT 3 0 ADDR 15 0 IVD 15 0 DATA 15 0 ADDR 22 20 ACC 2 0 ADDR 19 16 IQSTAT 3 0 ADDR 15 0 IVD 15 0 DATA 15 0 ADDR 22 0 DATA 15 0 Data...

Page 250: ...his multiplex timing ACCx are only shown in the current first access cycle IQSTATx and for read accesses IVDx follow in the next cycle If the access takes more than one bus cycle ACCx display NULL 0x0...

Page 251: ...1 iqstat 0 iqstat 1 ADDR 15 0 IVD 15 0 ivd 0 ivd 1 DATA 15 0 internal read z z z z z DATA 15 0 external read z data 0 z data 1 z RW 1 1 1 1 1 1 Table 5 13 Read Access 2 Cycles Access 0 Access 1 Bus c...

Page 252: ...0 addr 0 acc 0 addr 0 000 addr 1 acc 1 ADDR 19 16 IQSTAT 3 0 iqstat 1 iqstat 0 0000 ADDR 15 0 IVD 15 0 x x DATA 15 0 write data 0 x RW 0 0 0 0 1 1 Table 5 17 Write Access n 1 Cycles Access 0 Access 1...

Page 253: ...programmed for generation of a fixed number of 1 to 8 stretch cycles If the external wait feature is enabled the minimum number of additional stretch cycles is 2 An arbitrary amount of stretch cycles...

Page 254: ...ta direction signals as described below The data select signals are not available if using the external bus interface with an 8 bit data bus 5 4 5 1 Normal Expanded Mode In normal expanded mode the ex...

Page 255: ...5 8 at an even address 0 1 0 Out data odd In x Word write at an odd and odd 1 internal RAM address misaligned only in emulation modes 0 1 1 Out data odd 1 Out data odd Word read of data on DATA 15 0 a...

Page 256: ...ically to be used in emulator applications Taking the availability of the external wait feature into account the use cases are divided into four scenarios Normal expanded mode External wait feature di...

Page 257: ...efore the access is finished EWAIT can be held asserted as long as desired to stretch the access An access with 1 cycle stretch by EWAIT assertion is shown in Figure Example 1b Normal Expanded Mode St...

Page 258: ...igure 5 5 Application in Emulation Single Chip Mode The timing diagram for this operation is shown in Figure Example 2a Emulation Single Chip Mode Read Followed by Write The associated timing numbers...

Page 259: ...RB and RW signals Figure 5 6 shows the PRU connection with the available external bus signals in an emulator application Figure 5 6 Application in Emulation Expanded Mode The timings of accesses with...

Page 260: ...settings of 2 and 3 additional stretch cycles Timing considerations If no stretch cycle is added the timing is the same as in Emulation Single Chip Mode Because of an order from the United States Inte...

Page 261: ...omatically blocked if a higher level interrupt is being processed Interrupt requests configured to be handled by the XGATE module can be nested one level deep NOTE The HPRIO register and functionality...

Page 262: ...ses 0xFFFA 0xFFFE Determines the highest priority XGATE and interrupt vector requests drives the vector to the XGATE module or to the bus on CPU request respectively Wakes up the system from stop or w...

Page 263: ...It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs Please refer to Section 6 5 3 Wake Up from Stop or Wait Mode for details Fre...

Page 264: ...uest Route PRIOLVLn Priority Level bits from the channel configuration in the associated configuration register INT_XGPRIO XGATE Interrupt Priority IVBR Interrupt Vector Base IPL Interrupt Processing...

Page 265: ...guration Data Register 0 INT_CFDATA0 R W 0x0129 Interrupt Request Configuration Data Register 1 INT_CFDATA1 R W 0x012A Interrupt Request Configuration Data Register 2 INT_CFDATA2 R W 0x012B Interrupt...

Page 266: ...R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012A INT_CFDATA2 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012B INT_CFDATA3 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012C INT_CFDATA4 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012D INT_CFDATA5 R RQST...

Page 267: ...ree reset vectors 0xFFFA 0xFFFE Note If the BDM is active i e the CPU is in the process of executing BDM firmware code the contents of IVBR are ignored and the upper byte of the vector address is fixe...

Page 268: ...level 7 Address 0x0127 7 6 5 4 3 2 1 0 R INT_CFADDR 7 4 0 0 0 0 W Reset 0 0 0 1 0 0 0 0 Unimplemented or Reserved Figure 6 5 Interrupt Configuration Address Register INT_CFADDR Table 6 7 INT_CFADDR F...

Page 269: ...NT_CFDATA1 Address 0x012A 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure...

Page 270: ...a Register 5 INT_CFDATA5 Address 0x012E 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Re...

Page 271: ...also refer to Table 6 9 for available interrupt request priority levels Note Write accesses to configuration data registers of unused interrupt channels will be ignored and read accesses will return a...

Page 272: ...llowing conditions a The XGATE request enable bit must be 0 to have the CPU handle the interrupt request b The priority level must be set to non zero c The priority level must be greater than the curr...

Page 273: ...ers The XINT module contains priority decoders to determine the priority for all interrupt requests pending for the respective target There are two priority decoders one for each interrupt request tar...

Page 274: ...y the S12XCPU executes one instruction at a time Table 6 10 Exception Vector Map and Priority Vector Address 1 1 16 bits vector address based Source 0xFFFE Pin reset power on reset low voltage reset i...

Page 275: ...kable interrupt requests handled by the CPU I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority so that there can be up to seven nested I bit maskable i...

Page 276: ...If the X bit maskable interrupt request is used to wake up the MCU with the X bit in the CCR set the associated ISR is not called The CPU then resumes program execution with the instruction following...

Page 277: ...and register content extended modified Global page access functionality Enabled but not active out of reset in emulation modes if modes available CLKSW bit set out of reset in emulation modes if mode...

Page 278: ...have a control bit that allows suspending thefunction during background debug mode 7 1 2 1 Regular Run Modes All of these operations refer to the part in run mode and not being secured The BDM does no...

Page 279: ...e the ACK function The BDM is now ready to receive a new command 7 1 3 Block Diagram A block diagram of the BDM is shown in Figure 7 1 Figure 7 1 BDM Block Diagram 7 2 External Signal Description A si...

Page 280: ...mware ROM 1 0x7FFF10 0x7FFFFF BDM firmware ROM 240 Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x7FFF00 Reserved R X X X X X X 0 0 W 0x7FFF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE CLKSW UNSEC 0 W...

Page 281: ...mitted and executed 1 0 0 0 0 0 3 3 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased else it is 0 and can only be read if not secur...

Page 282: ...set by the firmware until after the non volatile memory erase verify tests are complete In emulation modes if modes available with the device secured the BDM operations are blocked 6 BDMACT BDM Active...

Page 283: ...ed this bit is only writable in special single chip mode from the BDM secure firmware It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put in...

Page 284: ...W holding register can be written to modify the CCR value 7 3 2 3 BDM CCR HIGH Holding Register BDMCCRH Figure 7 5 BDM CCR HIGH Holding Register BDMCCRH Read All modes through BDM operation when not s...

Page 285: ...egister Y stack pointer SP and program counter PC Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted see Section 7 4 3 BDM Hardware Commands and in...

Page 286: ...M bit in the BDM status BDMSTS register The ENBDM bit is set by writing to the BDM status BDMSTS register via the single wire interface using a hardware command such as WRITE_BD_BYTE After being enabl...

Page 287: ...locations unobtrusively even if the addresses conflict with the application memory map Table 7 6 Hardware Commands Command Opcode hex Data Description BACKGROUND 90 None Enter background mode if firmw...

Page 288: ...t 0x7FFF00 0x7FFFFF and the CPU begins executing the standard BDM firmware The standard BDM firmware watches for serial commands and executes them as they are received The firmware commands are shown...

Page 289: ...EAD_X 65 16 bit data out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT 42 16 bit data in Increment X index register by...

Page 290: ...ing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus On previous BDM modules this extra time could be hidden...

Page 291: ...ot typically drive the high level Since R C rise time could be unacceptably long the target system and host provide brief driven high speedup pulses to drive BKGD to a logic 1 The source of this speed...

Page 292: ...et Serial Bit Timing The receive cases are more complicated Figure 7 9 shows the host receiving a logic 1 from the target system Since the host is asynchronous to the target there is up to one clock c...

Page 293: ...Host Samples BKGD Pin Perceived Start of Bit Time BKGD Pin BDM Clock Target MCU Host Drive to BKGD Pin Target System Speedup Pulse High Impedance High Impedance Because of an order from the United St...

Page 294: ...the host controller when an issued command was successfully executed by the target This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin T...

Page 295: ...is grabbed free or stolen by the BDM and it executes the READ_BYTE operation Having retrieved the data the BDM issues an ACK pulse to the host controller indicating that the addressed byte is ready to...

Page 296: ...it has been executed command discarded and ACK not issued or if the UNTIL condition BDM active is just not reached yet Hence in any case where the ACK pulse of a command is not issued the possible pen...

Page 297: ...mmand NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior It is not recommended that this procedure be use...

Page 298: ...e hardware handshake protocol The target will issue the ACK pulse when a CPU command is executed by the CPU The ACK_ENABLE command itself also has the ACK pulse as a response ACK_DISABLE disables the...

Page 299: ...xecuted The ACK pulse related to this command could be aborted using the SYNC command 7 4 9 SYNC Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not n...

Page 300: ...Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running Hence possible timing relations between CPU code execution and...

Page 301: ...ency In this case the command could time out before the data is ready to be retrieved In order to allow the data to be retrieved even with a large clock frequency mismatch between BDM and CPU when the...

Page 302: ...ale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for im...

Page 303: ...Comparison NDB Dependency section Clarified effect TRIG has on state sequencer V03 19 24 Apr 2007 8 4 3 5 8 329 Clarified simultaneous arm and disarm effect V03 20 14 Apr 2007 8 3 2 7 8 315 Clarified...

Page 304: ...PU12X or XGATE buses Each comparator features selection of read or write access cycles Comparators B and D allow selection of byte or word access cycles Comparisons can be used as triggers for the sta...

Page 305: ...Thus breakpoints comparators and CPU12X bus tracing are disabled but XGATE bus monitoring accessing the S12XDBG registers including comparator registers is still possible While in active BDM or during...

Page 306: ...uction word being read into the instruction queue TAGLO See DUG TAGLO When instruction tagging is on tags the low half of the instruction word being read into the instruction queue TAGLO See DUG Uncon...

Page 307: ...K RW RWE SRC COMPE W 0x0029 DBGXAH R 0 Bit 22 21 20 19 18 17 Bit 16 W 0x002A DBGXAM R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002B DBGXAL R Bit 7 6 5 4 3 2 1 Bit 0 W 0x002C DBGXDH R Bit 15 14 13 12 11 10 9...

Page 308: ...Figure 8 3 Debug Control Register DBGC1 Table 8 5 DBGC1 Field Descriptions Field Description 7 ARM Arm Bit The ARM bit controls whether the S12XDBG module is armed This bit can be set and cleared by...

Page 309: ...n of the tracing session If tracing is not enabled the breakpoint is generated immediately Please refer to Section 8 4 7 for further details XGATE software breakpoints are independent of the DBGBRK bi...

Page 310: ...written to a one 0 External tag hit has not occurred 1 External tag hit has occurred 2 0 SSF 2 0 State Sequencer Flag Bits The SSF bits indicate in which state the State Sequencer is currently in Duri...

Page 311: ...ers If the corresponding SRC bit is set the comparator is mapped to the XGATE buses the TRANGE bits have no effect on the valid address range memory accesses within the whole memory map are traced See...

Page 312: ...GN Description 00 Trigger at end of stored data 01 Trigger before storing data 10 Trace buffer entries before and after trigger 11 Reserved Address 0x0023 7 6 5 4 3 2 1 0 R 0 0 0 0 CDCM ABCM W Reset 0...

Page 313: ...t 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W POR X X X X X X X X X X X X X X X X Other Resets Figure 8 7 Debug Trace Buffer Register DBGTB Table 8 18 DBGTB Field Descripti...

Page 314: ...y other system resets Thus should a reset occur during a debug session the DBGCNT register still indicates after the reset the number of valid trace buffer entries stored before the reset occurred The...

Page 315: ...f the comparator match control logic as depicted in Figure 8 1 and described in Section 8 3 2 8 1 Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control reg...

Page 316: ...to State2 Match2 triggers to State3 Other matches have no effect 1001 Match2 triggers to State3 Match0 triggers Final State Other matches have no effect 1010 Match1 triggers to State2 Match3 triggers...

Page 317: ...no effect 0111 Match1 triggers to State3 Match0 triggers Final State Other matches have no effect 1000 Match0 triggers to State1 Match2 triggers to State3 Other matches have no effect 1001 Match2 trig...

Page 318: ...h triggers to Final State 0011 Match0 triggers to State1 Other matches have no effect 0100 Match0 triggers to State2 Other matches have no effect 0101 Match0 triggers to Final State Match1 triggers to...

Page 319: ...register bits 7 and 6 differ depending upon which comparator registers are visible in the 8 byte window of the DBG module register address map Read Anytime See Table 8 29 for visible register encodin...

Page 320: ...either word or byte access size in comparison for the associated comparator This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set This bit position has NDB funct...

Page 321: ...mparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write 1 0 1 No match 1 1 0 No match 1 1 1 Read Address 0x0029 7 6 5 4 3 2 1...

Page 322: ...ther the selected comparator will compare the address bus bits 15 8 to a logic one or logic zero 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one...

Page 323: ...if the corresponding data mask bit is logic 1 This register is available only for comparators A and C 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one A...

Page 324: ...or Data High Mask Bits The Comparator data high mask bits control whether the selected comparator compares the data bus bits 15 8 to the corresponding comparator data compare bits This register is ava...

Page 325: ...r XGATE buses Each comparator compares the selected address bus with the address stored in DBGXAH DBGXAM and DBGXAL Furthermore comparators A and C also compare the data buses to the data stored in DB...

Page 326: ...an exact equivalence of address data bus with the value stored in the comparator address data registers Further qualification of the type of access R W word byte is possible Comparators A and C do not...

Page 327: ...cted value When matching on an equivalence NDB 0 each individual data bus bit position can be masked out by clearing the corresponding mask bit DBGxDHM DBGxDLM so that it is ignored in the comparison...

Page 328: ...ide Range CompAC_Addr address CompBD_Addr In the Inside Range comparator mode either comparator pair A and B or comparator pair C and D can be configured for range comparisons by the control register...

Page 329: ...s the execution stage of the instruction queue a taghit is generated by the CPU12X XGATE The state control register for the current state determines the next state for each trigger 8 4 3 3 External Ta...

Page 330: ...rom an internal trigger event then the ARM bit is cleared due to the hardware disarm 8 4 4 State Sequence Control Figure 8 22 State Sequencer Diagram The state sequencer allows a defined sequence of e...

Page 331: ...akpoint request to the CPU12X immediately 8 4 4 1 Final State On entering Final State a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field...

Page 332: ...re ending the tracing session irrespective of the number of lines stored before the trigger occurred then the S12XDBG module is disarmed and no more data is stored Using Mid trigger with tagging if th...

Page 333: ...hen the next instruction carried out is actually from the interrupt service routine The instruction at the destination address of the original program flow gets exectuted after the interrupt service r...

Page 334: ...s either in a free or opcode fetch cycle In this mode the XGATE program counter is also traced to provide a snapshot of the XGATE activity CXINF information byte bits indicate the type of XGATE activi...

Page 335: ...e time of the COF from the other source Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer CDATAL or XDATAL and the high byte is cleared When tracing word a...

Page 336: ...n of Thread 6 XSOT Start Of Thread Indicator This bit indicates that the corresponding stored address is a start of thread address This is only used in Normal and Loop1 mode tracing NOTE This bit only...

Page 337: ...nding stored address is a source or destination address This is only used in Normal and Loop1 mode tracing 0 Source address 1 Destination address 6 CVA Vector Indicator This bit indicates if the corre...

Page 338: ...d address corresponds to a read or write access This bit only contains valid information when tracing CPU12X activity in Detail Mode 0 Write Access 1 Read Access 4 COCF CPU12X Opcode Fetch Indicator T...

Page 339: ...h the instruction queue When a tagged instruction reaches the head of the queue a tag hit occurs and triggers the state sequencer Each comparator control register features a TAG bit which controls whe...

Page 340: ...E5 TAGLO MODA in the 7th or 8th bus cycle after reset enables the unconditional tagging function allowing immediate tagging via TAGHI TAGLO with breakpoint to BDM independent of the ARM BDM and DBGBRK...

Page 341: ...opcode reaches the execution stage of the instruction queue If a tracing session is selected by TSOURCE breakpoints are requested when the tracing session has completed thus if Begin or Mid aligned tr...

Page 342: ...as already started If a comparator tag hit occurs simultaneously with an external TAGHI TAGLO hit the state sequencer enters state0 TAGHI TAGLO triggers are always end aligned to end tracing immediate...

Page 343: ...command without program counter modification it will return to the instruction whose tag generated the breakpoint To avoid re triggering a breakpoint at the same location reconfigure the S12XDBG modul...

Page 344: ...Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for impor...

Page 345: ...ing routine that updates parameters stored in another section of the Flash memory The security features of the S12XE chip family in secure mode are Protect the content of non volatile memories Flash E...

Page 346: ...n in Table 9 3 Please refer to Section 9 1 5 1 Unsecuring the MCU Using the Backdoor Key Access for more information Table 9 2 Feature Availability in Unsecure and Secure Modes on S12XE Unsecure Mode...

Page 347: ...tion containing bootloader code then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state In this example the sec...

Page 348: ...ial single chip mode will cause the blank check to succeed and the options security byte can be programmed to unsecured state via BDM While the BDM is executing the blank check the BDM interface is co...

Page 349: ...the unsecured state after the next reset following the programming of the security bits to the unsecured value This method requires that The application software previously programmed into the microc...

Page 350: ...miconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import o...

Page 351: ...atures Section 10 6 Debug Mode Security Section 10 7 Security Instruction set Section 10 8 Instruction Set 10 1 1 Glossary of Terms XGATE Request A service request from a peripheral module which is di...

Page 352: ...lusively set by either the S12X_CPU or the XGATE see Section 10 4 4 Semaphores XGATE Thread A code sequence which is executed by the XGATE s RISC core after receiving an XGATE request XGATE Debug Mode...

Page 353: ...ock activity will be automatically stopped when the XGATE module is idle Freeze mode BDM active In freeze mode all clocks of the XGATE module may be stopped depending on the module configuration see S...

Page 354: ...Each description includes a standard register diagram with an associated figure number Details of register bits and field functions follow the register diagrams in bit order Register Name 15 14 13 12...

Page 355: ...GIF_40 W 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 0x0010 XGIF R XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30 W...

Page 356: ...0 Reserved R W 0x0021 Reserved R W 0x0022 XGR1 R XGR1 W 0x0024 XGR2 R XGR2 W 0x0026 XGR3 R XGR3 W 0x0028 XGR4 R XGR4 W 0x002A XGR5 R XGR5 W 0x002C XGR6 R XGR6 W 0x002E XGR7 R XGR7 W Unimplemented or R...

Page 357: ...it The XGFRZ bit can only be set or cleared if a 1 is written to the XGFRZM bit in the same register access Read This bit will always read 0 Write 0 Disable write access to the XGFRZ in the same bus c...

Page 358: ...INT module If the XGE bit is cleared pending XGATE requests will be ignored The thread that is executed by the RISC core while the XGE bit is cleared will continue to run Read 0 Incoming requests are...

Page 359: ...XGATE will always signal activity to the MCU Write 0 Only flag activity if not idle or in debug mode 1 Always signal XGATE activity 1 XGSWEF XGATE Software Error Flag This bit signals a software erro...

Page 360: ...ing Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 XGCHID 6 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 4 XGATE Channel ID Register XGCHID Table 10 3 XGCHID Field Descriptions Field Descript...

Page 361: ...Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 10 6 XGATE Initial Stack Pointer Select Register XGISPSEL Table 10 5 XGISPSEL Field Descriptions Field Description 1 0 XGISPSEL 1 0 Register sel...

Page 362: ...SP74 15 1 Initial Stack Pointer The XGISP74 register holds the initial value of RISC core register R7 for threads of priority 7 to 4 Module Base 0x0006 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGISP31...

Page 363: ...109 108 107 106 105 104 103 102 101 100 99 98 97 96 R XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60 W Reset 0 0 0 0 0 0...

Page 364: ...5 4 3 2 1 0 R XGIF_0F XGIF_0E XGIF_0D 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 10 10 XGIV Field Descriptions Field Description 127 9 XGIF 78 9...

Page 365: ...ter the software trigger mask controls the write access to the lower byte the software trigger bits These bits can be set or cleared if a 1 is written to the associated mask in the same bus cycle Refe...

Page 366: ...Semaphores Table 10 11 XGSWT Field Descriptions Field Description 15 8 XGSWTM 7 0 Software Trigger Mask These bits control the write access to the XGSWT bits Each XGSWT bit can only be written if a 1...

Page 367: ...n the same write access Only unlocked semaphores can be set A semaphore can be cleared by writing a 0 to the XGSEM bit and a 1 to the corresponding XGSEMM bit in the same write access Read 0 Semaphore...

Page 368: ...E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGPC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 14 XGATE Program Counter Register XGPC Table 10 14 XGPC Field Descriptions Field Description 15 0 XGPC...

Page 369: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 16 XGATE Register 2 XGR2 Table 10 16 XGR2 Field Descriptions Field Description 15 0 XGR2 15 0 XGATE Regi...

Page 370: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R XGR4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10 18 XGATE Register 4 XGR4 Table 10 18 XGR4 Field Descriptions Field Description 15 0 XGR4 15 0 XGATE Regi...

Page 371: ...by an XGATE request Then it executes a code sequence thread that is associated with the requested XGATE channel Each thread can run on a priority level ranging from 1 to 7 Refer to the S12X_INT Modul...

Page 372: ...8 Instruction Set It is able to access the MCU s internal memories and peripherals without blocking these resources from the S12X_CPU1 Whenever the S12X_CPU and the RISC core access the same resource...

Page 373: ...w flag V and the carry bit C The initial content of the condition code register is undefined 10 4 3 Memory Map The XGATE s RISC core is able to access an address space of 64K bytes The allocation of m...

Page 374: ...1 10 XGATE Semaphore Register XGSEM The RISC core does this through its SSEM and CSEM instructions IFigure 10 24 illustrates the valid state transitions 0000 unused 0024 0028 002C 0030 01E0 Code Data...

Page 375: ...ime the critical code sequence must be embedded in a semaphore lock release sequence as shown UNLOCKED LOCKED BY S12X_CPU LOCKED BY XGATE set_xgsem 1 is written to XGSEM n and 1 is written to XGSEMM n...

Page 376: ...des Illegal opcode fetches as well as illegal load and store accesses are defined on chip level Refer to the S12X_MMC Section for a detailed information NOTE When executing a branch BCC BCS a jump JAL...

Page 377: ...S12X_CPU software However these interrupts can also be routed to the S12X_CPU see S12X_INT Section and triggered by the XGATE software 6 Software error interrupt The software error interrupt signals t...

Page 378: ...to 127 can be initiated by writing to the XGCHID register even if they are not assigned to any peripheral module NOTE In Debug Mode the XGATE will ignore all requests from peripheral modules 10 6 1 0...

Page 379: ...s The S12X_DBG module is able to place tags on fetched opcodes The XGATE is able to enter debug mode right before a tagged opcode is executed see section 4 9 of the S12X_DBG Section Upon entering debu...

Page 380: ...for indexed addressing modes with register offset allowed range is R0 R7 RI Offset register for indexed addressing modes with register offset and post increment Allowed range is R0 R7 R0 is equivalent...

Page 381: ...R1 SUBL R2 2 subtracts an 8 bit value from register R2 LDH R3 3 loads an 8 bit immediate into the high byte of Register R3 CMPL R4 4 compares the low byte of register R4 with an immediate value 10 8 1...

Page 382: ...y the condition code flags are updated This addressing mode is used for all arithmetic and logical operations Examples ADC R5 R6 R7 R5 R6 R7 Carry SUB R5 R6 R7 R5 R6 R7 10 8 1 10 Relative Addressing 9...

Page 383: ...decremented by one In case of a word access it will be decremented by two Examples LDB R4 R1 R2 R2 1 loads a byte from R1 R2 into R4 STW R4 R1 R2 R2 2 stores R4 as a word to R1 R2 10 8 2 Instruction...

Page 384: ...inning of the next instruction Since instructions have a fixed 16 bit width the branch offsets are word aligned by shifting the offset value by 2 BEQ label if Z flag 1 branch to label An unconditional...

Page 385: ...2 SSEM Test and set a hardware semaphore 3 CSEM Clear a hardware semaphore 4 BRK Software breakpoint 5 NOP No Operation 6 RTS Terminate the current thread 10 8 3 Cycle Notation Table 10 23 show the XG...

Page 386: ...be interrupted by an interrupt request of higher priority 10 8 5 Instruction Glossary This section describes the XGATE instruction set in alphabetical order Table 10 23 Access Detail Notation V Vector...

Page 387: ...t if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 and Z was set before this operation cleared otherwise V Set if a two s complement overflow resulted from the operation cl...

Page 388: ...ared otherwise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RS1 15 RS2 15 RD 15 new RS1 15 RS2 15 RD 15 new Refer to...

Page 389: ...Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RD 15 old IMM8 7...

Page 390: ...N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the 8 bit operation cleared otherwise RD 15 old...

Page 391: ...ag CCR Effects Code and CPU Cycles AND Logical AND AND N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise Refer to ANDH instruction for IMM1...

Page 392: ...gical AND Immediate 8 bit Constant High Byte ANDH N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source F...

Page 393: ...ogical AND Immediate 8 bit Constant Low Byte ANDL N Z V C 0 N Set if bit 7 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source Fo...

Page 394: ...ent of RS is greater than 15 CCR Effects Code and CPU Cycles ASR Arithmetic Shift Right ASR N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise...

Page 395: ...e as BHS BCC N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BCC REL9 REL9 0 0 1 0 0 0 0 REL9 PP P Because of an order from the United...

Page 396: ...as BLO BCS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BCS REL9 REL9 0 0 1 0 0 0 1 REL9 PP P Because of an order from the United St...

Page 397: ...Q N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BEQ REL9 REL9 0 0 1 0 0 1 1 REL9 PP P Because of an order from the United States Inte...

Page 398: ...ract BFEXT N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address Mode Machine Code Cycles BFEXT...

Page 399: ...in the whole RS register at all CCR Effects Code and CPU Cycles BFFO Bit Field Find First One BFFO N Z V C 0 0 N 0 cleared Z Set if the result is 0000 cleared otherwise V 0 cleared C Set if RS 0000 1...

Page 400: ...PU Cycles BFINS Bit Field Insert BFINS N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address Mod...

Page 401: ...BFINSI Bit Field Insert and Invert BFINSI N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address...

Page 402: ...U Cycles BFINSX Bit Field Insert and XNOR BFINSX N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form A...

Page 403: ...h if Greater than or Equal to Zero BGE N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BGE REL9 REL9 0 0 1 1 0 1 0 REL9 PP P Because of...

Page 404: ...T Branch if Greater than Zero BGT N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BGT REL9 REL9 0 0 1 1 1 0 0 REL9 PP P Because of an o...

Page 405: ...les BHI Branch if Higher BHI N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BHI REL9 REL9 0 0 1 1 0 0 0 REL9 PP P Because of an order...

Page 406: ...nch if Higher or Same Same as BCC BHS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BHS REL9 REL9 0 0 1 0 0 0 0 REL9 PP P Because of...

Page 407: ...Immediate 8 bit Constant High Byte BITH N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source Form Addres...

Page 408: ...Immediate 8 bit Constant Low Byte BITL N Z V C 0 N Set if bit 7 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source Form Address...

Page 409: ...Branch if Less or Equal to Zero BLE N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BLE REL9 REL9 0 0 1 1 1 0 1 REL9 PP P Because of an...

Page 410: ...ranch if Carry Set Same as BCS BLO N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BLO REL9 REL9 0 0 1 0 0 0 1 REL9 PP P Because of an...

Page 411: ...BLS Branch if Lower or Same BLS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BLS REL9 REL9 0 0 1 1 0 0 1 REL9 PP P Because of an ord...

Page 412: ...T Branch if Lower than Zero BLT N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BLT REL9 REL9 0 0 1 1 0 1 1 REL9 PP P Because of an ord...

Page 413: ...MI N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BMI REL9 REL9 0 0 1 0 1 0 1 REL9 PP P Because of an order from the United States Int...

Page 414: ...BNE N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BNE REL9 REL9 0 0 1 0 0 1 0 REL9 PP P Because of an order from the United States I...

Page 415: ...L N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BPL REL9 REL9 0 0 1 0 1 0 0 REL9 PP P Because of an order from the United States Inte...

Page 416: ...ffected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BRA REL10 REL10 0 0 1 1 1 1 REL10 PP Because of an order from the United States International Trade Co...

Page 417: ...This instruction does not advance the program counter CCR Effects Code and CPU Cycles BRK Break BRK N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine...

Page 418: ...eared BVC N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BVC REL9 REL9 0 0 1 0 1 1 0 REL9 PP P Because of an order from the United Sta...

Page 419: ...Set BVS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles BVS REL9 REL9 0 0 1 0 1 1 1 REL9 PP P Because of an order from the United State...

Page 420: ...15 RS2 15 result 15 RS1 15 RS2 15 result 15 RD 15 IMM16 15 result 15 RD 15 IMM16 15 result 15 C Set if there is a carry from the bit 15 of the result cleared otherwise RS1 15 RS2 15 RS1 15 result 15...

Page 421: ...Compare Immediate 8 bit Constant Low Byte CMPL N Z V C N Set if bit 7 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V Set if a two s complement overflow resu...

Page 422: ...of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address Mode Machine Code Cycles COM RD RS TRI 0 0 0 1 0 RD 0 0 0 RS 1 1 P...

Page 423: ...cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RS1 15 RS2 15 result 15 RS1 15 RS2 15 result 15 C Set if there is a carry from the bit 15 of the re...

Page 424: ...R0 as destination register CCR Effects Code and CPU Cycles CPCH Compare Immediate 8 bit Constant with Carry High Byte CPCH N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the r...

Page 425: ...EM N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles CSEM IMM3 IMM3 0 0 0 0 0 IMM3 1 1 1 1 0 0 0 0 PA CSEM RS MON 0 0 0 0 0 RS 1 1 1 1 0...

Page 426: ...greater than 15 CCR Effects Code and CPU Cycles CSL Logical Shift Left with Carry CSL N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Se...

Page 427: ...s greater than 15 CCR Effects Code and CPU Cycles CSR Logical Shift Right with Carry CSR N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V...

Page 428: ...nk JAL N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles JAL RD MON 0 0 0 0 0 RD 1 1 1 1 0 1 1 0 PP Because of an order from the United S...

Page 429: ...e content of the register will not be incremented after the data move M RB RI RD L 00 RD H N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cyc...

Page 430: ...iate 8 bit Constant High Byte LDH N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles LDH RD IMM8 IMM8 1 1 1 1 1 RD IMM8 P Because of an or...

Page 431: ...ediate 8 bit Constant Low Byte LDL N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles LDL RD IMM8 IMM8 1 1 1 1 0 RD IMM8 P Because of an o...

Page 432: ...after the data move M RB RI RD N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles LDW RD RB OFFS5 IDO5 0 1 0 0 1 RD RB OFFS5 PR LDW RD RB...

Page 433: ...s greater than 15 CCR Effects Code and CPU Cycles LSL Logical Shift Left LSL N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Set if a two...

Page 434: ...is greater than 15 CCR Effects Code and CPU Cycles LSR Logical Shift Right LSR N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Set if a t...

Page 435: ...sult is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address Mode Machine Code Cycles MOV RD RS TRI 0 0 0 1 0 RD 0 0 0 RS 1 0 P Because of...

Page 436: ...se V Set if a two s complement overflow resulted from the operation cleared otherwise RS 15 RD 15 new C Set if there is a carry from the bit 15 of the result cleared otherwise RS 15 RD 15 new Source F...

Page 437: ...Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles NOP INH 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 P Because of an order from the United States International Trade Comm...

Page 438: ...Flag CCR Effects Code and CPU Cycles OR Logical OR OR N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise Refer to ORH instruction for IMM16...

Page 439: ...ogical OR Immediate 8 bit Constant High Byte ORH N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source Fo...

Page 440: ...Logical OR Immediate 8 bit Constant Low Byte ORL N Z V C 0 N Set if bit 7 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affected Source For...

Page 441: ...0 N 0 cleared Z Set if RD is 0000 cleared otherwise V 0 cleared C Set if the number of ones in the register RD is odd cleared otherwise Source Form Address Mode Machine Code Cycles PAR RD MON 0 0 0 0...

Page 442: ...ift will take place and the register RD will be unaffected however the condition code flags will be updated CCR Effects Code and CPU Cycles ROL Rotate Left ROL N Z V C 0 N Set if bit 15 of the result...

Page 443: ...ift will take place and the register RD will be unaffected however the condition code flags will be updated CCR Effects Code and CPU Cycles ROR Rotate Right ROR N Z V C 0 N Set if bit 15 of the result...

Page 444: ...N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles RTS INH 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 PA Because of an order from the United States Internat...

Page 445: ...N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 and Z was set before this operation cleared otherwise V Set if a two s complement overflow resulted from the...

Page 446: ...V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V 0 cleared C Not affected Source Form Address Mode Machine Code Cycles SEX RD MON 0 0 0 0 0...

Page 447: ...RS 15 7 is ignored NOTE Interrupt flags of reserved channels see Device User Guide can t be set CCR Effects Code and CPU Cycles SIF Set Interrupt Flag SIF N Z V C N Not affected Z Not affected V Not...

Page 448: ...Cycles SSEM Set Semaphore SSEM N Z V C N Not affected Z Not affected V Not affected C Set if semaphore is locked by the RISC core cleared otherwise Source Form Address Mode Machine Code Cycles SSEM I...

Page 449: ...ster is written to the memory RS L M RB RS 1 RS 1 RS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles STB RS RB OFFS5 IDO5 0 1 0 1 0 RS...

Page 450: ...written to the memory RS M RB RS 2 RS 2 RS N Z V C N Not affected Z Not affected V Not affected C Not affected Source Form Address Mode Machine Code Cycles STW RS RB OFFS5 IDO5 0 1 0 1 1 RS RB OFFS5 P...

Page 451: ...red otherwise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RS1 15 RS2 15 RD 15 new RS1 15 RS2 15 RD 15 new Refer to...

Page 452: ...N Z V C N Set if bit 15 of the result is set cleared otherwise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RD 15 ol...

Page 453: ...ise Z Set if the result is 0000 cleared otherwise V Set if a two s complement overflow resulted from the 8 bit operation cleared otherwise RD 15 old RD 15 new C Set if there is a carry from the bit 15...

Page 454: ...de and CPU Cycles TFR Transfer from and to Special Registers TFR Source Form Address Mode Machine Code Cycles TFR RD CCR CCR RD MON 0 0 0 0 0 RD 1 1 1 1 1 0 0 0 P TFR CCR RS RS CCR MON 0 0 0 0 0 RS 1...

Page 455: ...0000 cleared otherwise V Set if a two s complement overflow resulted from the operation cleared otherwise RS 15 result 15 C Set if there is a carry from the bit 15 of the result cleared otherwise RS1...

Page 456: ...t considered by the second instruction XNORH RD IMM16 15 8 Don t rely on the Z Flag CCR Effects Code and CPU Cycles XNOR Logical Exclusive NOR XNOR N Z V C 0 N Set if bit 15 of the result is set clear...

Page 457: ...gical Exclusive NOR Immediate 8 bit Constant High Byte XNORH N Z V C 0 N Set if bit 15 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affect...

Page 458: ...ogical Exclusive NOR Immediate 8 bit Constant Low Byte XNORL N Z V C 0 N Set if bit 7 of the result is set cleared otherwise Z Set if the 8 bit result is 00 cleared otherwise V 0 cleared C Not affecte...

Page 459: ...FFO RD RS 0 0 0 0 1 RD RS 1 0 0 0 0 ASR RD RS 0 0 0 0 1 RD RS 1 0 0 0 1 CSL RD RS 0 0 0 0 1 RD RS 1 0 0 1 0 CSR RD RS 0 0 0 0 1 RD RS 1 0 0 1 1 LSL RD RS 0 0 0 0 1 RD RS 1 0 1 0 0 LSR RD RS 0 0 0 0 1...

Page 460: ...RB RI 0 1 1 0 1 RD RB RI 0 1 STB RS RB RI 0 1 1 1 0 RS RB RI 0 1 STW RS RB RI 0 1 1 1 1 RS RB RI 0 1 LDB RD RB RI 0 1 1 0 0 RD RB RI 1 0 LDW RD RB RI 0 1 1 0 1 RD RB RI 1 0 STB RS RB RI 0 1 1 1 0 RS R...

Page 461: ...nitialization sequence 10 9 2 Code Example Transmit Hello World on SCI CPU S12X SYMBOLS SCI_REGS EQU 00C8 SCI register space SCIBDH EQU SCI_REGS 00 SCI Baud Rate Register SCIBDL EQU SCI_REGS 00 SCI Ba...

Page 462: ...1A XGATE Semaphore Register RPAGE EQU 0016 RAM_SIZE EQU 32 400 32k RAM RAM_START EQU 1000 RAM_START_XG EQU 10000 RAM_SIZE RAM_START_GLOB EQU 100000 RAM_SIZE XGATE_VECTORS EQU RAM_START XGATE_VECTORS_...

Page 463: ...interrupt flags LDD FFFF STD 2 X STD 2 X STD 2 X STD 2 X STD 2 X STD 2 X STD 2 X STD 2 X CLR XGISPSEL set vector base register MOVW XGATE_VECTORS_XG XGVBR MOVW FF00 XGSWT clear all software triggers...

Page 464: ..._REGS initiate SCI transmit STB R4 R2 SCIDRL SCI_REGS initiate SCI transmit CMPL R4 0D BEQ XGATE_CODE_DONE RTS XGATE_CODE_DONE LDL R4 00 disable SCI interrupts STB R4 R2 SCICR2 SCI_REGS LDL R3 XGATE_D...

Page 465: ...o 1 refer to Section 10 3 1 6 XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 XGISP31 Because of an order from the United States International Trade Commission BGA packaged product lines a...

Page 466: ...conductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or...

Page 467: ...xecution Clock switch for either Oscillator or PLL based system clocks Computer Operating Properly COP watchdog timer with time out clear window System Reset generation from the following possible sou...

Page 468: ...illator continues to run and most of the system and core clocks are stopped If the respective enable bits are set the COP and RTI will continue to run else they remain frozen Self Clock Mode Self Cloc...

Page 469: ...the MCU asynchronously to a known start up state As an open drain output it indicates that an system reset internal to MCU has been triggered ICRG Registers COP RESET RTI IPLL VDDPLL VSSPLL EXTAL XTAL...

Page 470: ...RF LOCKIF LOCK ILAF SCMIF SCM W 0x0004 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0005 CLKSEL R PLLSEL PSTP XCLKS 0 PLLWAI 0 RTIWAI COPWAI W 0x0006 PLLCTL R CME PLLON FM1 FM0 FSTWKP PRE PCE SCME W 0x000...

Page 471: ...e VCO gain for optimal stability and lock time For correct IPLL operation the VCOFRQ 1 0 bits have to be selected according to the actual target VCOCLK frequency as shown in Table 11 2 Setting the VCO...

Page 472: ...ocking and or insufficient stability 11 3 2 3 S12XECRG Post Divider Register POSTDIV The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK The count in the final divider divi...

Page 473: ...le Base 0x0003 7 6 5 4 3 2 1 0 R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W Reset 0 Note 1 Note 2 Note 3 0 0 0 0 1 PORF is set to 1 when a power on reset occurs Unaffected by system reset 2 LVRF is s...

Page 474: ...of IPLL lock condition This bit is cleared in Self Clock Mode Writes have no effect 0 VCOCLK is not within the desired tolerance of the target frequency 1 VCOCLK is within the desired tolerance of the...

Page 475: ...ed whenever RTIF is set 4 LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled 1 Interrupt will be requested whenever LOCKIF is set 1 SCMIE Self Clock Mode Interrupt Enable Bit 0 SC...

Page 476: ...increased power consumption 5 XCLKS Oscillator Configuration Status Bit This read only bit shows the oscillator configuration status 0 Loop controlled Pierce Oscillator is selected 1 External clock f...

Page 477: ...p from full stop mode the system will immediately resume operation in Self Clock Mode see Section 11 4 1 4 Clock Quality Checker The SCMIF flag will not be set The system will remain in Self Clock Mod...

Page 478: ...d divider value See Table 11 10 1 Decimal based divider value See Table 11 11 6 4 RTR 6 4 Real Time Interrupt Prescale Rate Select Bits These bits select the prescale rate for the RTI See Table 11 10...

Page 479: ...F 16x210 16x211 16x212 16x213 16x214 16x215 16x216 1 Denotes the default value out of reset This value should be used to disable the RTI to ensure future backwards compatibility Table 11 11 RTI Freque...

Page 480: ...03 550x103 1 1x106 2 2x106 1011 12 12x103 24x103 60x103 120x103 240x103 600x103 1 2x106 2 4x106 1100 13 13x103 26x103 65x103 130x103 260x103 650x103 1 3x106 2 6x106 1101 14 14x103 28x103 70x103 140x10...

Page 481: ...for the WCOP and CR 2 0 bits while writing the COPCTL register It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR 2 0 0 Write of WCOP and CR 2 0 has an effect with...

Page 482: ...es can alter the S12XECRG s functionality Read Always read 00 except in special modes 1 1 1 2 24 1 OSCCLK cycles are referenced from the previous COP time out reset writing 55 AA to the ARMCOP registe...

Page 483: ...ted between these writes but the sequence 55 AA must be completed prior to COP end of time out period to avoid a COP reset Sequences of 55 writes or sequences of AA writes are allowed When the WCOP bi...

Page 484: ...frequency do not exceed the specified bus frequency limit for the MCU If PLLSEL 1 then fBUS fPLL 2 IF POSTDIV 00 the fPLL is identical to fVCO divide by one Several examples of IPLL divider settings...

Page 485: ...request and then check the LOCK bit If interrupt requests are disabled software can poll the LOCK bit continuously during IPLL start up usually or at periodic intervals In either case only when the LO...

Page 486: ...ck But note that a CPU cycle corresponds to one Bus Clock IPLL clock mode is selected with PLLSEL bit in the CLKSEL register When selected the IPLL output clock drives SYSCLK for the main system inclu...

Page 487: ...re accurate check in addition to the clock monitor A clock quality check is triggered by any of the following events Power on reset POR Low voltage reset LVR Wake up from Full Stop Mode exit full stop...

Page 488: ...rmed An ongoing clock quality check could also cause a running IPLL fSCM and an active VREG during Pseudo Stop Mode 1 A Clock Monitor Reset will always set the SCME bit to logical 1 CHECK WINDOW OSC O...

Page 489: ...rrupt RTI The RTI can be used to generate a hardware interrupt at a fixed periodic rate If enabled by setting RTIE 1 this interrupt will occur at the rate selected by the RTICTL register The RTI runs...

Page 490: ...the MCU in a low power consumption stand by mode depending on setting of the individual bits in the CLKSEL register All individual Wait Mode configuration bits can be superposed This provides enhance...

Page 491: ...left again There are two ways to restart the MCU from Stop Mode 1 Any reset 2 Any interrupt If the MCU is woken up from Full Stop Mode by an interrupt and the fast wake up feature is enabled FSTWKP 1...

Page 492: ...struction STOP IRQ service FSTWKP 1 IRQ service STOP STOP IRQ service Oscillator Disabled Power Saving Self Clock Mode SCME 1 CPU resumes program execution immediately Interrupt Interrupt Interrupt Os...

Page 493: ...cy After 128 n SYSCLK cycles the RESET pin is released The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source Tabl...

Page 494: ...d leaves Self Clock Mode Since the clock quality checker is running in parallel to the reset generator the S12XECRG may leave Self Clock Mode while still completing the internal reset sequence 11 5 1...

Page 495: ...1 23 RESET Pin Held Low Externally 11 6 Interrupts The interrupts reset vectors requested by the S12XECRG are listed in Table 11 18 Refer to MCU specification for related vector addresses and prioriti...

Page 496: ...flag LOCKIF is set to1 when the LOCK condition has changed and is cleared to 0 by writing a 1 to the LOCKIF bit 11 6 1 3 Self Clock Mode Interrupt The S12XECRG generates a Self Clock Mode interrupt wh...

Page 497: ...external current limiting resistor Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode Low power consumption Operates from 1 8 V nominal supply Amplitude...

Page 498: ...itor 12 2 2 EXTAL and XTAL Input and Output Pins These pins provide the interface for either a crystal or a 1 8V CMOS compatible clock to control the internal clock generator circuitry EXTAL is the ex...

Page 499: ...or overtone resonators and crystals without a careful component selection Figure 12 3 Full Swing Pierce Oscillator Connections FSP mode selected Figure 12 4 External Clock Connections FSP mode selecte...

Page 500: ...n amplitude The output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer Electrical specification details are provided in the Electrical Characteristics ap...

Page 501: ...16 analog input channels Special conversions for VRH VRL VRL VRH 2 1 to 16 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on...

Page 502: ...ally generated clock ICLK as ATD clock For conversions during transition from Run to Stop Mode or vice versa the result is not written to the results register no CCF flag is set and no compare is done...

Page 503: ...Clock ATD Clock ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG0 See device specifi cation for availability ETRIG1 ETRIG2...

Page 504: ...ry of the ADC12B16C block 13 3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ADC12B16C 13 3 1 Module Memory Map Figure 13 2 gives a...

Page 505: ...ta DJM 0 and Section 13 3 2 12 2 Right Justified Result Data DJM 1 W 0x0018 ATDDR4 R See Section 13 3 2 12 1 Left Justified Result Data DJM 0 and Section 13 3 2 12 2 Right Justified Result Data DJM 1...

Page 506: ...n 13 3 2 12 1 Left Justified Result Data DJM 0 and Section 13 3 2 12 2 Right Justified Result Data DJM 1 W 0x002E ATDDR15 R See Section 13 3 2 12 1 Left Justified Result Data DJM 0 and Section 13 3 2...

Page 507: ...external trigger source to be either one of the AD channels or one of the ETRIG3 0 inputs See device specification for availability and connectivity of ETRIG3 0 inputs If a particular ETRIG3 0 input o...

Page 508: ...elect Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1...

Page 509: ...tware handler about changing A D values External trigger will not work while converting in stop mode For conversions during transition from Run to Stop Mode or vice versa the result is not written to...

Page 510: ...respective CCF flags is set Table 13 8 External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level Module Base 0x0003 7 6...

Page 511: ...esult registers hold valid data can be tracked using the conversion complete flags Fast flag clear mode may or may not be useful in a particular application to track valid data If this bit is one auto...

Page 512: ...1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 13 12 ATD Behavior in Freeze Mode Breakpoint FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish curre...

Page 513: ...sion clock period is itself a function of the prescaler value bits PRS4 0 Table 13 14 lists the available sample time lengths 4 0 PRS 4 0 ATD Clock Prescaler These 5 bits are the binary prescaler valu...

Page 514: ...2C S1C The first analog channel examined is determined by channel selection code CD CC CB CA control bits subsequent channels sampled in the sequence are determined by incrementing the channel selecti...

Page 515: ...AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 1 0 0 0 0 Reserved 0 0 0 1 Reserved 0 0 1 X Reserved 0 1 0 0 VRH 0 1 0 1 VRL 0 1 1 0 VRH VRL 2...

Page 516: ...CCF has been cleared This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels However it is also practical...

Page 517: ...versions of a sequence The sense of each comparison is determined by the CMPHT n bit in the ATDCMPHT register For each conversion number with CMPE n 1 do the following 1 Write compare value to ATDDRn...

Page 518: ...d CMPE n 1 in ATDCMPE the conversion complete flag is only set if comparison with ATDDRn is true and if ACMPIE 1 a compare interrupt will be requested In this case as the ATDDRn result register is use...

Page 519: ...uffer continuously If this bit is set while simultaneously using it as an analog port there is potentially increased power consumption because the digital input buffer maybe in the linear region Modul...

Page 520: ...the ATD result registers Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn Module Base 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0...

Page 521: ...l analog input channels to the sample and hold machine 13 4 1 3 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The resolution is program selectable at either 8 or...

Page 522: ...begins when the trigger is received Once ETRIGE is enabled conversions cannot be started by a write to ATDCTL5 but rather must be triggered externally If the level mode is active and the external tri...

Page 523: ...d at its input 13 5 Resets At reset the ADC12B16C is in a power down state The reset state of each individual bit is listed within the Register Description section see Section 13 3 2 Register Descript...

Page 524: ...eescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale fo...

Page 525: ...channels Four 8 bit pulse accumulators with 8 bit buffer registers associated with the four buffered IC channels Configurable also as two 16 bit pulse accumulators 16 bit modulus down counter with 8 b...

Page 526: ...OC5 IOC3 IOC4 IOC6 IOC7 PA Input Interrupt PA Overflow Interrupt Timer Overflow Interrupt Timer Channel 0 Interrupt Timer Channel 7 Interrupt Registers Bus Clock Channel 0 Channel 1 Channel 2 Channel...

Page 527: ...output compare for channel 2 14 2 7 IOC1 Input Capture and Output Compare Channel 1 This pin serves as input capture or output compare for channel 1 14 2 8 IOC0 Input Capture and Output Compare Channe...

Page 528: ...0x0004 TCNT High R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x0005 TCNT Low R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 W 0x0007...

Page 529: ...4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0016 TC3 High R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0017 TC3 Low R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0018 TC4 High R Bit 15 Bit 14...

Page 530: ...ACNT0 W 0x0024 PACN1 R PACNT7 15 PACNT6 14 PACNT5 13 PACNT4 12 PACNT3 11 PACNT2 10 PACNT1 9 PACNT0 8 W 0x0025 PACN0 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0026 MCCTL R MCZI MODM...

Page 531: ...2H2 PA2H1 PA2H0 W 0x0034 PA1H R PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1H0 W 0x0035 PA0H R PA0H7 PA0H6 PA0H5 PA0H4 PA0H3 PA0H2 PA0H1 PA0H0 W 0x0036 MCCNT High R MCCNT15 MCCNT14 MCCNT13 MCCNT12 MC...

Page 532: ...se 0x0000 7 6 5 4 3 2 1 0 R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W Reset 0 0 0 0 0 0 0 0 Figure 14 3 Timer Input Capture Output Compare Register TIOS Table 14 2 TIOS Field Descriptions Field Descri...

Page 533: ...channel occurs at the same time as the successful output compare then the forced output compare action will take precedence and the interrupt flag will not get set Module Base 0x0002 7 6 5 4 3 2 1 0 R...

Page 534: ...hannel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register Module Base 0x0004 15 14 13 12...

Page 535: ...Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer including the counter Can be used for reducing power consumption 1 Allows the timer to function normally Note If for...

Page 536: ...of the delay counter PR0 PR1 and PR2 bits of the TSCR2 register are used for timer counter prescaler selection MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler se...

Page 537: ...TCTL1 TCTL2 Field Descriptions Field Description OM 7 0 7 5 3 1 OMx Output Mode OLx Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of...

Page 538: ...pture edge detector circuits for each input capture channel The four pairs of control bits in TCTL4 also configure the input capture edge control for the four 8 bit pulse accumulators PAC0 PAC3 EDG0B...

Page 539: ...Reset Enable This bit allows the timer counter to be reset by a successful channel 7 output compare This mode of operation is similar to an up counting modulus counter 0 Counter reset disabled and co...

Page 540: ...a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Mod...

Page 541: ...ference TFFCA bit in Section 14 3 2 6 Timer System Control Register 1 TSCR1 14 3 2 14 Timer Input Capture Output Compare Registers 0 7 Module Base 0x000F 7 6 5 4 3 2 1 0 R TOF 0 0 0 0 0 0 0 W Reset 0...

Page 542: ...r 1 Low TC1 Module Base 0x0014 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure 14 23 Timer Input Capture Output Compare Register 2 High TC2...

Page 543: ...r 4 Low TC4 Module Base 0x001A 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure 14 29 Timer Input Capture Output Compare Register 5 High TC5...

Page 544: ...0 0 0 0 0 0 0 Figure 14 32 Timer Input Capture Output Compare Register 6 Low TC6 Module Base 0x001E 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0...

Page 545: ...to be incremented 1 Rising edges on PT7 pin cause the count to be incremented For PAMOD bit 1 gated time accumulation mode 0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and...

Page 546: ...LK 256 as timer counter clock frequency 1 1 Use PACLK 65536 as timer counter clock frequency Module Base 0x0021 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 PAOVF PAIF W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserv...

Page 547: ...imultaneously write takes priority and the register is not incremented 14 3 2 18 Pulse Accumulators Count Registers PACN1 and PACN0 Module Base 0x0022 7 6 5 4 3 2 1 0 R PACNT7 15 PACNT6 14 PACNT5 13 P...

Page 548: ...clocking pulse and write to the registers occurs simultaneously write takes priority and the register is not incremented 14 3 2 19 16 Bit Modulus Down Counter Control Register MCCTL Read Anytime Writ...

Page 549: ...registers The pulse accumulators will be automatically cleared when the latch action occurs Writing zero to this bit has no effect Read of this bit will always return zero 3 FLMC Force Load Register...

Page 550: ...aches 0x0000 The flag indicates when interrupt conditions have occurred The flag can be cleared via the normal flag clearing mechanism writing a one to the flag or via the fast flag clearing mechanism...

Page 551: ...r is set to 0 only bits DLY0 DLY1 are used to calculate the delay Table 14 27 shows the delay settings in this case When the PRNT bit of TSCR1 register is set to 1 all bits are used to set a more prec...

Page 552: ...bus clock cycles 0 0 0 0 0 1 1 0 28 bus clock cycles 0 0 0 0 0 1 1 1 32 bus clock cycles 0 0 0 0 1 1 1 1 64 bus clock cycles 0 0 0 1 1 1 1 1 128 bus clock cycles 0 0 1 1 1 1 1 1 256 bus clock cycles...

Page 553: ...o values in the capture and holding registers instead of generating an interrupt for every capture By setting TFMOD in queue mode when NOVWx bit is set and the corresponding capture and holding regist...

Page 554: ...tch mode is enabled Latching function occurs when modulus down counter reaches zero or a zero is written into the count register MCCNT see Section 14 4 1 1 2 Buffered IC Channels With a latching event...

Page 555: ...le 14 33 shows some selection examples in this case The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero Table 14 33 Pr...

Page 556: ...1 is set to 1 Table 14 35 shows some possible division rates The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register...

Page 557: ...led 0 16 bit pulse accumulator system disabled 8 bit PAC1 and PAC0 can be enabled when their related enable bits in ICPAR are set 1 Pulse accumulator B system enabled The two 8 bit pulse accumulators...

Page 558: ...ccumulator 1 PAC1 overflows from 0x00FF to 0x0000 When PACMX 1 PBOVF bit can also be set if 8 bit pulse accumulator 1 PAC1 reaches 0x00FF and an active edge follows on PT1 Module Base 0x0032 7 6 5 4 3...

Page 559: ...count register If the RDMCL bit is set reads of the MCCNT will return the contents of the load register Module Base 0x0035 7 6 5 4 3 2 1 0 R PA0H7 PA0H6 PA0H5 PA0H4 PA0H3 PA0H2 PA0H1 PA0H0 W Reset 0 0...

Page 560: ...ps The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an immediate load is desired 14 3 2 32 Timer Input Capture Holding Registers 0 3 TCxH Module Base 0x...

Page 561: ...3 TC2 TC1 TC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 63 Timer Input Capture Holding Register 2 Low TC2H Module Base 0x003E 15 14 13 12 11 10 9 8 R TC15 TC14 TC13 TC12 TC11 TC10 TC...

Page 562: ...1 1 IC Channels 14 4 Functional Description This section provides a complete functional description of the ECT block detailing the operation of the design from the end user perspective in a number of...

Page 563: ...are Reg Comparator TC5 Capture Compare Reg Comparator TC6 Capture Compare Reg Comparator TC7 Capture Compare Reg Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Delay T...

Page 564: ...ure Compare Reg Comparator TC6 Capture Compare Reg Comparator TC7 Capture Compare Reg Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Delay TC1H Hold Reg TC2H Hold Reg...

Page 565: ...CH1 LATCH3 LATCH2 LATQ BUFEN Queue Mode Read TC3H Hold Reg Read TC2H Hold Reg Read TC1H Hold Reg Read TC0H Hold Reg Down Counter SH04 SH15 SH26 SH37 Timer Prescaler 16 Bit Free Running Main Timer Dela...

Page 566: ...UFEN Queue Mode Read TC3H Hold Reg Read TC2H Hold Reg Read TC1H Hold Reg Read TC0H Hold Reg Down Counter SH04 SH15 SH26 SH37 Timer Prescaler 16 Bit Free Running Main Timer Delay Counter Delay Counter...

Page 567: ...r Delay Counter P3 Edge Detector Delay Counter PA0H Holding 0 8 Bit PAC1 PACN1 0 8 Bit PAC2 PACN2 PA2H Holding 0 8 Bit PAC3 PACN3 PA3H Holding 8 Bit PAC0 PACN0 8 12 16 1024 8 12 16 1024 8 12 16 1024 8...

Page 568: ...escaled Clock PCLK Interrupt MUX PAMOD Edge Detector PACA Delay Counter Interrupt PACB 8 Bit PAC3 PACN3 8 Bit PAC2 PACN2 8 Bit PAC1 PACN1 8 Bit PAC0 PACN0 Px Edge Delay 16 Bit Main Timer TCx Input TCx...

Page 569: ...of four standard IC registers and four buffered IC channels An IC register is empty when it has been read or latched into the holding register A holding register is empty when it has been read 14 4 1...

Page 570: ...or value to its holding register 14 4 1 1 3 Delayed IC Channels There are four delay counters in this module associated with IC channels 0 3 The use of this feature is explained in the diagram and not...

Page 571: ...the bus frequency or Eclk The user can prevent the 8 bit pulse accumulators from counting further than 0x00FF by utilizing the PACMX control bit in the ICSYS register In this case a value of 0x00FF me...

Page 572: ...h the ECT modes of operation as described below The flags cannot be cleared via the normal flag clearing mechanism This fast flag clearing mechanism has the advantage of eliminating the software overh...

Page 573: ...description section Section 14 3 Memory Map and Register Definition which details the registers and their bit fields Because of an order from the United States International Trade Commission BGA pack...

Page 574: ...asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller 14 4 3 4 Pulse Accumulator A Input Interrupt This active high output will be as...

Page 575: ...asserted by the module to request a timer overflow interrupt to be serviced by the system controller Because of an order from the United States International Trade Commission BGA packaged product lin...

Page 576: ...cale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for i...

Page 577: ...re limited by a maximum bus capacitance of 400 pF 15 1 1 Features The IIC module has the following key features Compatible with I2C bus standard Multi master operation Software programmable for one of...

Page 578: ...external pins 15 2 1 IIC_SCL Serial Clock Line Pin This is the bidirectional serial clock line SCL of the module compatible to the IIC bus specification 15 2 2 IIC_SDA Serial Data Line Pin This is the...

Page 579: ...Bit 0 0x0000 IBAD R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 W 0x0001 IBFD R IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 W 0x0002 IBCR R IBEN IBIE MS SL Tx Rx TXAK 0 0 IBSWAI W RSTA 0x0003 IBSR R TCF IAAS IBB...

Page 580: ...IBC3 IBC2 IBC1 IBC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15 4 IIC Bus Frequency Divider Register IBFD Table 15 3 IBFD Field Descriptions Field Description 7 0 IBC 7 0 I Bus Clock R...

Page 581: ...he SDA hold time IBC7 6 defines the multiplier factor MUL The values of MUL are shown in the Table 15 6 Table 15 5 Prescale Divider Encoding IBC5 3 bin scl2start clocks scl2stop clocks scl2tap clocks...

Page 582: ...internal bus frequencies This happens when the internal bus cycle length becomes equal to a pad delay The SCL input is used for clock arbitration of multiple masters Thus after each SCL edge is inter...

Page 583: ...240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2A 448 65...

Page 584: ...18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4A 72 18 28 38 4B 80 18 32 42 4C 88 22 36 46 4D 96 22 40 50 4E 112 26 48 58 4F 136 26 60 70 50 96 18 36 50 51 112 18...

Page 585: ...42 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148 1154 75 2560 386 1276 1282 76 3072 514 1532 1538 77 3840 514 1916 1922 78 2560 258 1276 1282 79 3072 258 1532 1538 7A...

Page 586: ...216 228 9B 512 68 248 260 9C 576 100 280 292 9D 640 100 312 324 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 132 440 452 A3 1024 132 504 516 A4 1152 196 568 580 A5...

Page 587: ...28 3576 3588 BB 8192 1028 4088 4100 BC 9216 1540 4600 4612 BD 10240 1540 5112 5124 BE 12288 2052 6136 6148 BF 15360 2052 7672 7684 Module Base 0x0002 7 6 5 4 3 2 1 0 R IBEN IBIE MS SL Tx Rx TXAK 0 0 I...

Page 588: ...nerated on the bus and the master mode is selected When this bit is changed from 1 to 0 a STOP signal is generated and the operation mode changes from master to slave A STOP signal should only be gene...

Page 589: ...ched with the calling address or it receives the general call address with GCEN 1 this bit is set The CPU is interrupted provided the IBIE is set Then the CPU needs to check the SRW bit and set its Tx...

Page 590: ...the calling address sent from the master This bit is only valid when the I bus is in slave mode a complete address transfer has occurred with an address match and no other transfers have been initiat...

Page 591: ...Figure 15 10 Module Base 0x0005 7 6 5 4 3 2 1 0 R GCEN ADTYPE 0 0 0 ADR10 ADR9 ADR8 W Reset 0 0 0 0 0 0 0 0 Figure 15 9 IIC Bus Control Register 2 IBCR2 Table 15 10 IBCR2 Field Descriptions Field Des...

Page 592: ...eir idle states Figure 15 11 Start and Stop Conditions CL DA Start Signal Ack Bit 1 2 3 4 5 6 7 8 MSB LSB 1 2 3 4 5 6 7 8 MSB LSB No CL DA 1 2 3 4 5 6 7 8 MSB LSB 1 2 5 6 7 8 MSB LSB Repeated 3 4 9 9...

Page 593: ...y while SCL is low and must be held stable while SCL is high as shown in Figure 15 10 There is one clock pulse on SCL for each data bit the MSB being transferred first Each data byte has to be followe...

Page 594: ...atus bit is set by hardware to indicate loss of arbitration 15 4 1 7 Clock Synchronization Because wire AND logic is performed on SCL line a high to low transition on SCL line affects all the devices...

Page 595: ...ated START Sr the first slave address is transmitted again but the R W is 1 meaning that the slave is acted as a transmitter 15 4 1 11 General Call Address To broadcast using a general call a device m...

Page 596: ...e IIC module enters a power conservation state during wait mode In the later case any transmission or reception in progress stops at wait mode entry 15 4 4 Operation in Stop Mode The IIC is inactive i...

Page 597: ...TART After completion of the initialization procedure serial data can be transmitted by selecting the master transmitter mode If the device is connected to a multi master bus system the state of the I...

Page 598: ...not valid the Tx Rx bit in the control register should be read to determine the direction of the current transfer The following is an example of a software response by a master transmitter in the inte...

Page 599: ...nsmitting the next byte of data Setting RXAK means an end of data signal from the master receiver after which it must be switched from transmitter mode to receiver mode by software A dummy read then r...

Page 600: ...nal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS 1 IAAS 1 SRW 1 TX RX Set TX Mode Write Data To IBDR Set RX Mode Dummy Read From IBDR ACK From Receiver Tx Next Byte R...

Page 601: ...address the point of the data array in interrupt routine must be reset after it s addressed Because of an order from the United States International Trade Commission BGA packaged product lines and pa...

Page 602: ...2 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescal...

Page 603: ...ments of a vehicle serial data bus real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth MSCAN uses an advanced buffer arrangement resul...

Page 604: ...with FIFO storage scheme Three transmit buffers with internal prioritization using a local priority concept Flexible maskable identifier filter supports two full size 32 bit extended identifier filte...

Page 605: ...Functional Description for details Listen Only Mode MSCAN Sleep Mode MSCAN Initialization Mode MSCAN Power Down Mode 16 2 External Signal Description The MSCAN uses two external pins 16 2 1 RXCAN CAN...

Page 606: ...ase address of the MSCAN module is determined at the MCU level when the MCU is defined The register decode map is fixed and begins at the first address of the module address offset The detailed regist...

Page 607: ...ABTAK0 W 0x000A CANTBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x000B CANIDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 W 0x000C Reserved R 0 0 0 0 0 0 0 0 W 0x000D CANMISC R 0 0 0 0 0 0 0 BOHOLD W 0x000E CANRXERR...

Page 608: ...gister is writable again as soon as the initialization mode is exited INITRQ 0 and INITAK 0 Read Anytime 0x0014 0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018 0x001B CANIDAR4 7 R AC7 AC6 A...

Page 609: ...ses to be clocked during wait mode 4 SYNCH Synchronized Status This read only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process It is...

Page 610: ...en tries to synchronize to the CAN bus If the MSCAN is not in bus off state it synchronizes after 11 consecutive recessive bits on the CAN bus if the MSCAN is in bus off state it continues to wait for...

Page 611: ...nores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message Both transmit and receive interrupts are generated 0 Loopback self test disabled...

Page 612: ...ANBTR1 CANIDAC CANIDAR0 CANIDAR7 and CANIDMR0 CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode 0 Running The MSCAN operates normally 1 Initialization mode active The MS...

Page 613: ...value of the single bit positioned at the sample point If SAMP 1 the resulting bit value is determined by using majority rule on the three total samples For higher bit rates it is recommended that onl...

Page 614: ...ble 16 36 for valid settings 0 0 1 2 Tq clock cycles 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 16 9 Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycl...

Page 615: ...interrupt is pending while this flag is set CSCIF provides a blocking interrupt That guarantees that the receiver transmitter status bits RSTAT TSTAT are only updated when no CAN status change interr...

Page 616: ...F flag must be cleared to release the buffer A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer RxFG If not masked a receive interrupt is pending while this flag i...

Page 617: ...tate is defined by the CAN standard see Bosch CAN 2 0A B protocol specification for only transmitters Because the only possible state change for the transmitter from bus off to TxOK also forces the re...

Page 618: ...after the message is sent successfully The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request see Section 16 3 2 9 MSCAN Transmitter Mes...

Page 619: ...Anytime when not in initialization mode Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 16 11 MSCAN Transmitter Interrupt Enable Regis...

Page 620: ...MSCAN Transmitter Message Abort Acknowledge Register CANTAAK are set and a transmit interrupt occurs if enabled The CPU cannot reset ABTRQx ABTRQx is reset whenever the associated TXE flag is set 0 N...

Page 621: ...f CANTBSEL results in 0b0000_0010 because only the lowest numbered bit position set to 1 is presented This mechanism eases the application software the selection of the next available Tx buffer LDAA C...

Page 622: ...de The CPU sets these flags to define the identifier acceptance filter organization see Section 16 4 3 Identifier Acceptance Filter Table 16 18 summarizes the different settings In filter closed mode...

Page 623: ...this register when in special modes can alter the MSCAN functionality 16 3 2 14 MSCAN Miscellaneous Register CANMISC This register provides additional features Table 16 19 Identifier Acceptance Hit In...

Page 624: ...ANMISC Table 16 20 CANMISC Register Field Descriptions Field Description 0 BOHOLD Bus off State Hold Until User Request If BORM is set in Section 16 3 2 2 MSCAN Control Register 1 CANCTL1 this bit ind...

Page 625: ...fer The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers accepted otherwise the message is overwritten by the next message...

Page 626: ...AC0 W Reset 0 0 0 0 0 0 0 0 Figure 16 20 MSCAN Identifier Acceptance Registers First Bank CANIDAR0 CANIDAR3 Table 16 21 CANIDAR0 CANIDAR3 Register Field Descriptions Field Description 7 0 AC 7 0 Acce...

Page 627: ...3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0...

Page 628: ...22 MSCAN Identifier Mask Registers First Bank CANIDMR0 CANIDMR3 Table 16 23 CANIDMR0 CANIDMR3 Register Field Descriptions Field Description 7 0 AM 7 0 Acceptance Mask Bits If a particular bit in this...

Page 629: ...MR7 Register Field Descriptions Field Description 7 0 AM 7 0 Acceptance Mask Bits If a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance...

Page 630: ...for extended identifiers The mapping of standard identifiers into the IDR registers is shown in Figure 16 25 All bits of the receive and transmit buffers are x out of reset because of RAM based imple...

Page 631: ...DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X7 DSR3 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X8 DSR4 R DB7 DB6 DB5...

Page 632: ...ined 0x00XX because of RAM based implementation 16 3 3 1 Identifier Registers IDR0 IDR3 The identifier registers for an extended format identifier consist of a total of 32 bits ID 28 0 SRR IDE and RTR...

Page 633: ...mitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number 4 SRR Substitute Remote Request This fixed recessive...

Page 634: ...ing Table 16 29 IDR3 Register Field Descriptions Extended Field Description 7 1 ID 6 0 Extended Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most si...

Page 635: ...s the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number See also ID bi...

Page 636: ...fier Register 2 Standard Mapping Module Base 0x00X3 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 16 33 Identifier Register 3 Standard Mapping Module Base 0x0004 DSR0 0x0005 DS...

Page 637: ...ta length code contains the number of bytes data byte count of the respective message During the transmission of a remote frame the data length code is transmitted as programmed while the number of tr...

Page 638: ...ansmit buffer is selected in CANTBSEL see Section 16 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL 16 3 3 5 Time Stamp Register TSRH TSRL If the TIME bit is enabled the MSCAN will write a t...

Page 639: ...onal Description 16 4 1 General This section provides a complete functional description of the MSCAN It describes each of the features and modes listed in the introduction Module Base 0xXXXF 7 6 5 4 3...

Page 640: ...a broad range of network applications MSCAN Rx0 Rx1 CAN Receive Transmit Engine CPU12 Memory Mapped I O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxF...

Page 641: ...d in Section 16 4 2 2 Transmit Structures 16 4 2 2 Transmit Structures The MSCAN triple transmit buffer scheme optimizes real time performance by allowing multiple messages to be set up in advance The...

Page 642: ...ent ABTAK 0 16 4 2 3 Receive Structures The received messages are stored in a five stage input FIFO The five message buffers are alternately mapped into a single memory area see Figure 16 39 The backg...

Page 643: ...n be marked don t care in the MSCAN identifier mask registers see Section 16 3 2 18 MSCAN Identifier Mask Registers CANIDMR0 CANIDMR7 A filter hit is indicated to the application software by a set rec...

Page 644: ...ifier Figure 16 42 shows how the first 32 bit filter bank CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 produces filter 0 to 3 hits Similarly the second filter bank CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 produces...

Page 645: ...CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted Filter 0 Hit AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted Filter 1 Hit CAN 2 0B Extended Iden...

Page 646: ...CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted Filter 1 Hit ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3...

Page 647: ...16 4 5 6 MSCAN Power Down Mode and Section 16 4 5 5 MSCAN Initialization Mode The MSCAN enable bit CANE is writable only once in normal system operation modes which provides further protection agains...

Page 648: ...es the PROP_SEG and the PHASE_SEG1 of the CAN standard It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta Time Segment 2 This segment represents the PHASE_SEG2 of th...

Page 649: ...4 4 2 Special Modes The MSCAN module behaves as described within this specification in all special system operation modes Table 16 35 Time Segment Syntax Syntax Description SYNC_SEG System expects tr...

Page 650: ...ption compared to normal mode sleep and power down mode In sleep mode power consumption is reduced by stopping all clocks except those to access the registers from the CPU side In power down mode all...

Page 651: ...he MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the value of the SLPRQ SLPAK and CSWAI bits Table 16 37 16 4 5 4 MSCAN Sleep Mode The CPU...

Page 652: ...message can be read and RXF can be cleared Shifting a new message into the foreground buffer of the receiver FIFO RxFG does not take place while in sleep mode It is possible to access the transmit buf...

Page 653: ...N into sleep mode SLPRQ 1 and SLPAK 1 before setting the INITRQ bit in the CANCTL0 register Otherwise the abort of an on going message can cause an error condition and can impact other CAN bus devices...

Page 654: ...rwise the abort of an ongoing message can cause an error condition and impact other CAN bus devices In power down mode all clocks are stopped and no registers can be accessed If the MSCAN was not in s...

Page 655: ...ely after receiving the EOF symbol The RXF flag is set If there are multiple messages in the receiver FIFO the RXF flag is set as soon as the next message is shifted to the foreground buffer 16 4 7 4...

Page 656: ...ipulation instructions BSET must not be used to clear interrupt flags These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service rou...

Page 657: ...e bits on the CAN bus See the Bosch CAN specification for details If the MSCAN is configured for user request BORM set in Section 16 3 2 2 MSCAN Control Register 1 CANCTL1 the recovery from bus off st...

Page 658: ...9 658 Freescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Free...

Page 659: ...ger peripheral modules Start of timer channels can be aligned to each other 17 1 3 Modes of Operation Refer to the device overview for a detailed explanation of the chip modes Table 17 1 Revision Hist...

Page 660: ...ram Figure 17 1 shows a block diagram of the PIT module Figure 17 1 PIT24B8C Block Diagram 17 2 External Signal Description The PIT module has no external pins Time Out 0 Time Out 1 Time Out 2 Time Ou...

Page 661: ...E4 PINTE3 PINTE2 PINTE1 PINTE0 W 0x0005 PITTF R PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 W 0x0006 PITMTLD0 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W 0x0007 PITMTLD1 R PMTLD7 PMTLD6 PM...

Page 662: ...0x0015 PITLD3 Low R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0016 PITCNT3 High R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0017 PITCNT3 Low R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PC...

Page 663: ...PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0023 PITCNT6 Low R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0024 PITLD7 High R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0025 PITLD7 Low R PLD7...

Page 664: ...odule when in wait mode 5 PITFRZ PIT Counter Freeze while in Freeze Mode Bit When during debugging a breakpoint freeze mode is encountered it is useful in many cases to freeze the PIT counters to avoi...

Page 665: ...0 0 0 0 Figure 17 5 PIT Channel Enable Register PITCE Table 17 4 PITCE Field Descriptions Field Description 7 0 PCE 7 0 PIT Enable Bits for Timer Channel 7 0 These bits enable the PIT channels 7 0 If...

Page 666: ...0 0 0 0 0 0 0 0 Figure 17 7 PIT Interrupt Enable Register PITINTE Table 17 6 PITINTE Field Descriptions Field Description 7 0 PINTE 7 0 PIT Time out Interrupt Enable Bits for Timer Channel 7 0 These b...

Page 667: ...0 0 0 0 0 0 Figure 17 9 PIT Micro Timer Load Register 0 PITMTLD0 Module Base 0x0007 7 6 5 4 3 2 1 0 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W Reset 0 0 0 0 0 0 0 0 Figure 17 10 PIT M...

Page 668: ...ad Register 3 PITLD3 Module Base 0x0018 0x0019 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 669: ...alue if an immediate load is desired Module Base 0x000A 0x000B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT 15 PCNT 14 PCNT 13 PCNT 12 PCNT 11 PCNT 10 PCN T9 PCN T8 PCN T7 PCN T6 PCN T5 PCN T4 PCN T3...

Page 670: ...0 0 0 Figure 17 24 PIT Count Register 5 PITCNT5 Module Base 0x0022 0x0023 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT 15 PCNT 14 PCNT 13 PCNT 12 PCNT 11 PCNT 10 PCN T9 PCN T8 PCN T7 PCN T6 PCN T5 PC...

Page 671: ...are Trigger 8 Interrupt Request 8 PITLD1 Register PITCNT1 Register Timer 1 1 PFLT1 PITLD2 Register PITCNT2 Register Timer 2 2 PFLT2 PITLD3 Register PITCNT3 Register Timer 3 PFLT3 time out 0 PFLMT 1 0...

Page 672: ...r counter and the connected 8 bit micro timer counter have counted to zero the PITLD register is reloaded and the corresponding time out flag PTF in the PIT time out flag PITTF register is set as show...

Page 673: ...g periodic ATD conversion please refer to the device overview for the mapping of PITTRIG 7 0 signals to peripheral modules Whenever a timer channel time out is reached the corresponding PTF flag is se...

Page 674: ...constructs that compile to BSET instructions BSET flag_register mask must not be used for flag clearing because BSET is a read modify write instruction which writes back the bit wise or of the flag_re...

Page 675: ...A loop until interrupt Channel 0 Interupt Routine CH0_ISR LDAA PITTF 8 bit read of PIT time out flags MOVB 01 PITTF clear PIT channel 0 time out flag RTI return to MAIN Because of an order from the Un...

Page 676: ...escale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for...

Page 677: ...r peripheral modules Start of timer channels can be aligned to each other 18 1 3 Modes of Operation Refer to the device overview for a detailed explanation of the chip modes Table 18 1 Revision Histor...

Page 678: ...s a block diagram of the PIT module Figure 18 1 PIT24B4C Block Diagram 18 2 External Signal Description The PIT module has no external pins 18 3 Register Definition This section consists of register d...

Page 679: ...PITLD0 High R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0009 PITLD0 Low R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x000A PITCNT0 High R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8...

Page 680: ...LD10 PLD9 PLD8 W 0x0015 PITLD3 Low R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0016 PITCNT3 High R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0017 PITCNT3 Low R PCNT7 PCNT6 PCNT5 PCNT...

Page 681: ...reeze mode 1 0 PFLMT 1 0 PIT Force Load Bits for Micro Timer 1 0 These bits have only an effect if the corresponding micro timer is active and if the PIT module is enabled PITE set Writing a one into...

Page 682: ...ble the PIT channels 3 0 If PCE is cleared the PIT channel is disabled and the corresponding flag bit in the PITTF register is cleared When PCE is set and if the PIT module is enabled PITE 1 the 16 bi...

Page 683: ...bit timer counts with micro time base 1 Module Base 0x0004 7 6 5 4 3 2 1 0 R 0 0 0 0 PINTE3 PINTE2 PINTE1 PINTE0 W Reset 0 0 0 0 0 0 0 0 Figure 18 7 PIT Interrupt Enable Register PITINTE Table 18 6 P...

Page 684: ...fect If flag clearing by writing a one and flag setting happen in the same bus clock cycle the flag remains set The flag bits are cleared if the PIT module is disabled or if the corresponding timer ch...

Page 685: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 11 PIT Load Register 0 PITLD0 Module Base 0x000C 0x000D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PL...

Page 686: ...0 0 0 0 0 0 0 0 0 0 Figure 18 15 PIT Count Register 0 PITCNT0 Module Base 0x000E 0x000F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT 15 PCNT 14 PCNT 13 PCNT 12 PCNT 11 PCNT 10 PCN T9 PCN T8 PCN T7 PC...

Page 687: ...rate two micro time bases As soon as a micro time base is selected for an enabled timer channel the corresponding micro timer modulus down counter will load its start value as specified in the PITMTLD...

Page 688: ...ividually be restarted by writing a one to the corresponding force load micro timer PFLMT bits in the PIT control and force load micro timer PITCFLMT register The 16 bit timers can individually be res...

Page 689: ...etting trigger timing and a restart with force load is shown in Figure 18 20 18 5 Initialization 18 5 1 Startup Set the configuration registers before the PITE bit in the PITCFLMT register is set Befo...

Page 690: ...nge to be selected LDS RAMEND load stack pointer to top of RAM MOVW CH0_ISR VEC_PIT_CH0 Change value of channel 0 ISR adr Start PIT Initialization CLR PITCFLMT disable PIT MOVB 01 PITCE enable timer c...

Page 691: ...els with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable disable for each channel Software selection of PWM duty pulse polarity for each channel Perio...

Page 692: ...Description The PWM module has a total of 8 external pins Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty Counter Channel 5 Period and Duty Counter Channel 4 Period and Duty...

Page 693: ...registers and register bits in the PWM module The special purpose registers and register bit functions that are not normally available to device end users such as factory test control registers and r...

Page 694: ...6 5 4 3 2 1 Bit 0 0x0000 PWME R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W 0x0001 PWMPOL R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W 0x0002 PWMCLK R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2...

Page 695: ...5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0012 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0013 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0014 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001...

Page 696: ...4 3 2 1 Bit 0 W 0x001E PWMDTY2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001F PWMDTY3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0010 PWMDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0021 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0022 PWMDT...

Page 697: ...PWM output bit 7 when its clock source begins its next cycle 6 PWME6 Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled 1 Pulse width channel 6 is enabled The pulse modulated signal beco...

Page 698: ...idth Channel 1 Enable 0 Pulse width channel 1 is disabled 1 Pulse width channel 1 is enabled The pulse modulated signal becomes available at PWM output bit 1 when its clock source begins its next cycl...

Page 699: ...nnel 6 5 PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5 1 Clock SA is the clock source for PWM channel 5 4 PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A...

Page 700: ...channels 2 3 6 or 7 These three bits determine the rate of clock B as shown in Table 19 2 2 0 PCKA 2 0 Prescaler Select for Clock A Clock A is one of two clock sources which can be used for channels...

Page 701: ...ter provides for various control of the PWM module Read Anytime Write Anytime 1 1 1 Bus clock 128 Module Base 0x0004 7 6 5 4 3 2 1 0 R CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 W Reset 0 0 0 0 0 0 0 0 F...

Page 702: ...to create one 16 bit PWM channel Channel 4 becomes the high order byte and channel 5 becomes the low order byte Channel 5 output pin is used as the output for this 16 bit PWM bit 5 of port PWMP Chann...

Page 703: ...this bit is set whenever the MCU is in freeze mode the input clock to the prescaler is disabled This feature is useful during emulation as it allows the PWM function to be suspended In this way the c...

Page 704: ...PWM Scale B Register PWMSCLB PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB Clock SB is generated by taking clock B dividing it by the value in the PWMSCLB regis...

Page 705: ...to up the immediate load of both duty and period registers with values from the buffers and the output to change according to the polarity bit The counter is also cleared at the end of the effective p...

Page 706: ...OTE Reads of this register return the most recent value written Reads do not necessarily return the value of the currently active period due to the double buffering scheme See Section 19 4 2 3 PWM Per...

Page 707: ...e value of the currently active duty due to the double buffering scheme See Section 19 4 2 3 PWM Period and Duty for more information NOTE Depending on the polarity bit the duty registers will contain...

Page 708: ...ved Figure 19 17 PWM Shutdown Register PWMSDN Field Description 7 PWMIF PWM Interrupt Flag Any change from passive to asserted active state or from active to passive state will be flagged by setting t...

Page 709: ...abled PWME7 0 0 This is useful for reducing power by disabling the prescale counter Clock A and clock B are scaled values of the input clock The value is software selectable for both clock A and clock...

Page 710: ...s it further with a user programmable value and then divides this by 2 The rates available for clock SA are software selectable to be clock A divided by 2 4 6 8 or 512 in increments of divide by 2 Sim...

Page 711: ...lock Clock Select M U X PCLK0 Clock to PWM Ch 0 M U X PCLK2 Clock to PWM Ch 2 M U X PCLK1 Clock to PWM Ch 1 M U X PCLK4 Clock to PWM Ch 4 M U X PCLK5 Clock to PWM Ch 5 M U X PCLK6 Clock to PWM Ch 6 M...

Page 712: ...o PWMSCLA or PWMSCLB causes the associated 8 bit down counter to be re loaded Otherwise when changing rates the counter would have to count down to 01 before counting at the proper rate Forcing the as...

Page 713: ...An exception to this is when channels are concatenated Refer to Section 19 4 2 7 PWM 16 Bit Functions for more detail NOTE The first PWM cycle after enabling the channel can be irregular On the front...

Page 714: ...is possible to know where the count is with respect to the duty value and software can be used to make adjustments NOTE When forcing a new period or duty into effect immediately an irregular PWM cycl...

Page 715: ...ted with the CAEx bits in the PWMCAE register If the CAEx bit is cleared CAEx 0 the corresponding PWM output will be left aligned In left aligned output mode the 8 bit counter is configured as an up c...

Page 716: ...consider the following case Clock Source E where E 10 MHz 100 ns period PPOLx 0 PWMPERx 4 PWMDTYx 1 PWMx Frequency 10 MHz 4 2 5 MHz PWMx Period 400 ns PWMx Duty Cycle 3 4 100 75 The output waveform ge...

Page 717: ...Period and Duty The counter counts from 0 up to the value in the period register and then back down to 0 Thus the effective period is PWMPERx 2 NOTE Changing the PWM output mode from left aligned to...

Page 718: ...nnel 6 registers become the high order bytes of the double byte channel as shown in Figure 19 24 Similarly when channels 4 and 5 are concatenated channel 4 registers become the high order bytes of the...

Page 719: ...to either the low or high order byte of the counter will reset the 16 bit counter Reads of the 16 bit counter must be made by 16 bit access to maintain data coherency PWMCNT6 PWCNT7 PWM7 Clock Source...

Page 720: ...or just following reset are described within this section The 8 bit up down counter is configured as an up counter out of reset All the channels are disabled and all the counters do not count Table 1...

Page 721: ...wait mode with the PSWAI bit set the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set A description of the registers involved a...

Page 722: ...cale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for i...

Page 723: ...20 4 6 6 20 754 20 4 5 5 20 746 20 4 2 20 739 20 4 4 20 741 Opened three new registers using a Mode bit Added Wakeup capability on Receive Input Added LIN transmit collision detect capability Added L...

Page 724: ...ess mark wakeup Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receive wa...

Page 725: ...gh This input is ignored when the receiver is disabled and should be terminated to a known voltage 20 3 Memory Map and Register Definition This section provides a detailed description of all the SCI r...

Page 726: ...2 1 Bit 0 0x0000 SCIBDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR...

Page 727: ...set to zero 2 These registers are accessible if the AMAP bit in the SCISR2 register is set to one Module Base 0x0000 7 6 5 4 3 2 1 0 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0...

Page 728: ...lculating the baud rate are When IREN 0 then SCI baud rate SCI bus clock 16 x SBR 12 0 When IREN 1 then SCI baud rate SCI bus clock 32 x SBR 12 1 Note The baud rate generator is disabled after reset a...

Page 729: ...Line Type Bit ILT determines when the receiver starts counting logic 1s as idle character bits The counting begins either after the start bit or after the stop bit If the count begins after the start...

Page 730: ...eaningful if BERRIF 1 0 A low input was sampled when a high was expected 1 A high input reassembled when a low was expected 1 BERRIF Bit Error Interrupt Flag BERRIF is asserted when the bit error dete...

Page 731: ...s enabled Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 0 0 0 0 BERRM1 BERRM0 BKDFE W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 8 SCI Alternative Control Register 2 SCIACR2 Table 20 8 SCIACR2...

Page 732: ...Bit RIE enables the receive data register full flag RDRF or the overrun flag OR to generate interrupt requests 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled 4 ILIE...

Page 733: ...her receiver interrupt requests Normally hardware wakes the receiver by automatically clearing RWU 0 SBK Send Break Bit Toggling SBK sends one break character 10 or 11 logic 0s respectively 13 or 14 l...

Page 734: ...r IDLE by reading SCI status register 1 SCISR1 with IDLE set and then reading SCI data register low SCIDRL 0 Receiver input is either active now or has never become active since the IDLE flag was last...

Page 735: ...ield Description 7 AMAP Alternative Map This bit controls which registers sharing the same address space are accessible In the reset condition the SCI behaves as previous versions Setting AMAP 1 allow...

Page 736: ...ng 1 Break character is 13 or 14 bit long 1 TXDIR Transmitter Pin Data Direction in Single Wire Mode This bit determines whether the TXD pin is going to be used as an input or output in the single wir...

Page 737: ...ween the CPU and remote devices including other CPUs The SCI transmitter and receiver operate independently although they use the same baud rate generator The CPU monitors the status of the SCI writes...

Page 738: ...h are encoded by the infrared submodule to transmit a narrow pulse SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Baud Rate Generator SBR12 SBR0 Bus Transmit Contro...

Page 739: ...zero bit and no pulse for a one bit The narrow pulse is sent in the middle of the bit with a duration of 1 32 1 16 3 16 or 1 4 of a bit time A narrow high pulse is transmitted for a zero bit when TXP...

Page 740: ...its Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 1 1 1 The address bit identifies the frame as an address character See Section 20 4 6 6 Receiver Wakeup 0 1 Table 20 15 Example of 9 Bit D...

Page 741: ...ror Integer division of the bus clock may not give the exact target frequency Table 20 16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz When IREN 0 then SCI b...

Page 742: ...through the TXD pin after it has prefaced them with a start bit and appended them with a stop bit The SCI data registers SCIDRH and SCIDRL are the write only buffers between the internal data bus and...

Page 743: ...il the TDRE flag has been cleared 3 Repeat step 2 for each subsequent transmission NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH L which...

Page 744: ...ers into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 a...

Page 745: ...synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1 If the TE bit is cleared during a transmission the TXD pin becomes idle after completion...

Page 746: ...rror interrupt flag BERRIF will be set No further transmissions will take place until the BERRIF is cleared Figure 20 19 Timing Diagram Bit Error Detection If the bit error detect feature is disabled...

Page 747: ...ame shifts into the receive shift register the data portion of the frame transfers to the SCI data register The receive data register full flag RDRF in SCI status register 1 SCISR1 becomes set All 1s...

Page 748: ...ssible start bit occurs the RT clock begins to count to 16 Figure 20 21 Receiver Data Sampling To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Figure 2...

Page 749: ...rt bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 20 19 summarizes the results of the stop bit samples Table 20 18 Data Bit Recovery RT8 RT...

Page 750: ...thin the bit time and data recovery is successful Figure 20 23 Start Bit Search Example 2 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT1...

Page 751: ...bit time it does set the noise flag Figure 20 25 Start Bit Search Example 4 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 R...

Page 752: ...flag because a break character has no stop bit The FE flag is set at the same time that the RDRF flag is set 20 4 6 5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or...

Page 753: ...th the misaligned character shown in Figure 20 28 the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles 144 RTt cycles The maximum pe...

Page 754: ...cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 176 170 176 x 100 3 40 20 4 6 6 Receiver Wakeup To enable the SC...

Page 755: ...clears the RWU bit and wakes up the SCI The logic 1 in the MSB position marks a frame as an address frame that contains addressing information All receivers evaluate the addressing information and th...

Page 756: ...OOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 SCICR1 Setting the LOOPS bit disables the path from the RXD pin to the receiver Clearin...

Page 757: ...s section describes the interrupt originated by the SCI block The MCU must service the interrupt requests Table 20 20 lists the eight interrupt sources of the SCI 20 5 3 1 Description of Interrupt Ope...

Page 758: ...is queued and ready to be sent 20 5 3 1 3 RDRF Description The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register A RDRF interrupt indicates that the...

Page 759: ...terrupt is set when a break signal was received Clear BKDIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if break detect feature is disabled 20 5 4 Recover...

Page 760: ...eescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale fo...

Page 761: ...l clock with programmable polarity and phase Control of SPI operation during wait mode 21 1 3 Modes of Operation The SPI functions in three modes run wait and stop Table 21 1 Revision History Revision...

Page 762: ...ter Stop mode The SPI is inactive in stop mode for reduced power consumption If the SPI is configured as a master any transmission in progress stops but is resumed after CPU goes into run mode If the...

Page 763: ...ve data when it is configured as master SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control...

Page 764: ...a base address and an address offset The base address is defined at the SoC level and the address offset is defined at the module level Reads from the reserved bits return zeros and writes to the rese...

Page 765: ...able This bit enables SPI interrupt requests if SPTEF flag is set 0 SPTEF interrupt disabled 1 SPTEF interrupt enabled 4 MSTR SPI Master Slave Mode Select Bit This bit selects whether the SPI operates...

Page 766: ...s bit will abort a transmission in progress and force the SPI system into idle state 0 Data is transferred most significant bit first 1 Data is transferred least significant bit first Table 21 3 SS In...

Page 767: ...rt pin is not used by the SPI 1 SS port pin with MODF feature 3 BIDIROE Output Enable in the Bidirectional Mode of Operation This bit controls the MOSI and MISO output buffer of the SPI when in bidire...

Page 768: ...ter mode a change of these bits will abort a transmission in progress and force the SPI system into idle state 2 0 SPR 2 0 SPI Baud Rate Selection Bits These bits specify the SPI baud rates as shown i...

Page 769: ...it s 1 0 0 0 1 1 80 312 5 kbit s 1 0 0 1 0 0 160 156 25 kbit s 1 0 0 1 0 1 320 78 13 kbit s 1 0 0 1 1 0 640 39 06 kbit s 1 0 0 1 1 1 1280 19 53 kbit s 1 0 1 0 0 0 12 2 08333 Mbit s 1 0 1 0 0 1 24 1 04...

Page 770: ...ansmit Empty Interrupt Flag If set this bit indicates that the transmit data register is empty For information about clearing this bit and placing data into the transmit data register please refer to...

Page 771: ...SPIDRH SPIDRL XFRW Bit SPTEF Interrupt Flag Clearing Sequence 0 Read SPISR with SPTEF 1 then Write to SPIDRL 1 1 Any write to SPIDRH or SPIDRL with SPTEF 0 is effectively ignored 1 Read SPISR with SP...

Page 772: ...register until the start of another transmission The data in the SPIDR does not change If SPIF is set and valid data is in the receive shift register and SPIF is serviced before the start of a third...

Page 773: ...e dedicated to the SPI function as Slave select SS Serial clock SCK Master out slave in MOSI Master in slave out MISO Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received...

Page 774: ...ister1 is set master mode is selected when the MSTR bit is clear slave mode is selected NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will dest...

Page 775: ...21 4 2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear Serial clock In slave mode SCK is the SPI clock input from the master MISO MOSI pin In slave mode...

Page 776: ...ransferred into the SPI data register To indicate transfer is complete the SPIF flag in the SPI status register is set NOTE A change of the bits CPOL CPHA SSOE LSBFE MODFEN SPC0 or BIDIROE with SPC0 s...

Page 777: ...pin of the master to the serial input pin on the slave This process continues for a total of 16 edges on the SCK line with data being latched on odd numbered edges and shifted on even numbered edges...

Page 778: ...ansfer begins here for tT tl tL Minimum 1 2 SCK tI tL tL Minimum leading time before the first SCK edge tT Minimum trailing time after the last SCK edge tI Minimum idling time between transfers minimu...

Page 779: ...irst data bit to the serial data input pin of the master A half SCK cycle later the second edge appears on the SCK pin This is the latching edge for both the master and slave 1 n depends on the select...

Page 780: ...gram because the SCK MISO and MOSI pins are connected directly between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS li...

Page 781: ...e baud rate preselection bits SPPR2 SPPR0 and the value in the baud rate selection bits SPR2 SPR0 The module clock divisor equation is shown in Equation 21 3 BaudRateDivisor SPPR 1 2 SPR 1 Eqn 21 3 tL...

Page 782: ...omatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices When SS output is selected the SS output pin is connected to...

Page 783: ...Error Conditions The SPI has one error condition Mode fault error 21 4 6 1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master it indicates a system error where more t...

Page 784: ...stem is in a low power disabled state SPI registers remain accessible but clocks to the core of this module are disabled 21 4 7 2 SPI in Wait Mode SPI operation in wait mode depends upon the state of...

Page 785: ...and signals are described in Section 21 3 Memory Map and Register Definition which details the registers and their bit fields If a data transmission occurs in slave mode after reset without a write t...

Page 786: ...PI Status Register SPISR 21 4 7 5 3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data After SPTEF is set it does not clear until it is serviced SPTEF has an automatic clearing...

Page 787: ...re registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 22 1 1 Features The...

Page 788: ...ze Timer counter keep on running unless TSFRZ in TSCR 0x0006 is set to 1 Wait Counters keep on running unless TSWAI in TSCR 0x0006 is set to 1 Normal Timer counter keep on running unless TEN in TSCR 0...

Page 789: ...hannel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Ou...

Page 790: ...elect CLK0 CLK1 4 1 MUX TIMCLK PACLK PACLK 256 PACLK 65536 Prescaled clock PCLK Timer clock Interrupt MUX PAMOD PACNT PTn Edge detector 16 bit Main Timer TCn Input Capture Reg Set CnF Interrupt Becaus...

Page 791: ...utput Compare Channel 5 Pin This pin serves as input capture or output compare for channel 5 22 2 4 IOC4 Input Capture and Output Compare Channel 4 Pin This pin serves as input capture or output compa...

Page 792: ...Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details of register bit an...

Page 793: ...0 0 0 0 0 W 0x0010 0x001F TCxH TCxL R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0020 PACTL R 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI...

Page 794: ...e 22 2 TIOS Field Descriptions Field Description 7 0 IOS 7 0 Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture 1 The corresponding channel acts...

Page 795: ...nd interrupt flag won t get set Module Base 0x0002 7 6 5 4 3 2 1 0 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W Reset 0 0 0 0 0 0 0 0 Figure 22 8 Output Compare 7 Mask Register OC7M Table 22 4...

Page 796: ...lock Table 22 5 OC7D Field Descriptions Field Description 7 0 OC7D 7 0 Output Compare 7 Data A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer po...

Page 797: ...counter whenever the MCU is in freeze mode This is useful for emulation TSFRZ does not stop the pulse accumulator 4 TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normall...

Page 798: ...nly takes effect when in output compare mode When set it takes precedence over forced output compare but not channel 7 override events 0 Toggle output compare pin on overflow feature disabled 1 Toggle...

Page 799: ...are encoded to specify the output action to be taken as a result of a successful OCx compare When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note To enable outpu...

Page 800: ...on any edge rising or falling Module Base 0x000C 7 6 5 4 3 2 1 0 R C7I C6I C5I C4I C3I C2I C1I C0I W Reset 0 0 0 0 0 0 0 0 Figure 22 18 Timer Interrupt Enable Register TIE Table 22 12 TIE Field Descri...

Page 801: ...compare 7 event This mode of operation is similar to an up counting modulus counter 0 Counter reset inhibited and counter free runs 1 Counter reset by a successful output compare 7 If TC7 0x0000 and...

Page 802: ...C0F W Reset 0 0 0 0 0 0 0 0 Figure 22 20 Main Timer Interrupt Flag 1 TFLG1 Table 22 15 TRLG1 Field Descriptions Field Description 7 0 C 7 0 F Input Capture Output Compare Channel x Flag These flags a...

Page 803: ...Timer Overflow Flag Set when 16 bit free running timer overflows from 0xFFFF to 0x0000 Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 is set to one See...

Page 804: ...Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator is enabled PAEN 1 For PAMOD bit 0 event counter mode See Table 22 18 0 Falling edges on IOC7 pin cause the count to be...

Page 805: ...r Timer module must stay enabled TEN 1 while clearing these bits Table 22 18 Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div by 64 clock enabled with pin high level 1 1 Div...

Page 806: ...PAFLG register while TEN bit of TSCR1 register is set to one 0 PAIF Pulse Accumulator Input edge Flag Set when the selected edge is detected at the IOC7 input pin In event mode the event edge triggers...

Page 807: ...Compare Pin Disconnect Bits 0 Enables the timer channel port Ouptut Compare action will occur on the channel pin These bits do not affect the input capture or pulse accumulator functions 1 Disables th...

Page 808: ...in this case The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero Table 22 23 Precision Timer Prescaler Selection Examp...

Page 809: ...E DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNEL7 TC7 16 BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM OL7 TOV7 EDG1A EDG1B EDG7A EDG7B EDG0B TCRE PAIF CLEAR COUNTER PAIF PAI...

Page 810: ...n and frequency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin if the corresponding OCPDx bit is set t...

Page 811: ...the count NOTE The PACNT input and timer channel 7 use the same pin IOC7 To use the IOC7 disconnect it from the output logic by clearing the channel 7 output mode and output level bits OM7 and OL7 Als...

Page 812: ...request a timer channel 7 0 interrupt to be serviced by the system controller 22 6 2 Pulse Accumulator Input Interrupt PAOVI This active high output will be asserted by the module to request a timer...

Page 813: ...ll be asserted by the module to request a timer overflow interrupt to be serviced by the system controller Because of an order from the United States International Trade Commission BGA packaged produc...

Page 814: ...reescale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale f...

Page 815: ...rent sourcing capability Features LVD low voltage detect LVR low voltage reset and POR power on reset and HTD High Temperature Detect are available The API is available 2 Reduced power mode RPM MCU is...

Page 816: ...ble This mode must be used to disable the chip internal regulator VREG_3V3 i e to bypass the VREG_3V3 to use external supplies 23 1 3 Block Diagram Figure 23 1 shows the function principle of VREG_3V3...

Page 817: ...w Voltage Detect LVR Low Voltage Reset POR Power on Reset HTD High Temperature Detect C HTI HTD API API API Auto Periodical Interrupt VBG API Rate Select Bus Clock REG2 REG1 REG3 VDDF VSSA VDDX Becaus...

Page 818: ...pplied from these signals A chip external decoupling capacitor 100 nF 220 nF X7R ceramic between VDDA and VSSA can further improve the quality of this supply 23 2 3 VDD VSS Regulator Output1 Core Logi...

Page 819: ...PLL must be provided externally Shutdown mode is entered with VREGEN being low If VREGEN is high the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode For the connectivity of VREGEN...

Page 820: ...0 0 VSEL VAE HTEN HTDS HTIE HTIF W 0x02F1 VREGCTRL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 VREGAPIC L R APICLK 0 0 APIFES APIEA APIFE APIE APIF W 0x02F3 VREGAPIT R R APITR5 APITR4 APITR3 APITR2 APITR1 API...

Page 821: ...cted to Analog to Digital Converter channel 1 Voltage selected by VSEL can be accessed internally 3 HTEN High Temperature Enable Bit If set the temperature sense is enabled 0 The temperature sense is...

Page 822: ...rce for the API Writable only if APIFE 0 APICLK cannot be changed if APIFE is set by the same write operation 0 Autonomous periodical interrupt clock used as source 1 Bus clock used as source 4 APIES...

Page 823: ...ut has occurred 0x02F3 7 6 5 4 3 2 1 0 R APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 0 0 W Reset 01 01 01 01 01 01 0 0 1 Reset value is either 0 or preset by factory See Section 1 Device Overview for de...

Page 824: ...9 for details of the effect of the autonomous periodical interrupt rate bits Writable only if APIFE 0 of VREGAPICL register Table 23 9 Selectable Autonomous Periodical Interrupt Periods APICLK APIR 1...

Page 825: ...0 0 01 01 01 01 1 Reset value is either 0 or preset by factory See Section 1 Device Overview for details Unimplemented or Reserved Figure 23 9 VREGHTTR Table 23 10 VREGHTTR field descriptions Field D...

Page 826: ...ge by an operational amplifier The amplified input voltage difference drives the gate of an output transistor 23 4 2 2 Reduced Power Mode In Reduced Power Mode the gate of the output transistor is con...

Page 827: ...gister block of VREG_3V3 and further digital functionality needed to control the operating modes CTRL also represents the interface to the digital core logic 23 4 8 Autonomous Periodical Interrupt API...

Page 828: ...d signals are provided in Section 23 3 Memory Map and Register Definition Possible reset sources are listed in Table 23 12 23 4 10 Description of Reset Operation 23 4 10 1 Power On Reset POR During ch...

Page 829: ...THTID An interrupt indicated by flag HTIF 1 is triggered by any change of the status bit HTDS if interrupt enable bit HTIE 1 NOTE On entering the Reduced Power Mode the HTIF is not cleared by the VRE...

Page 830: ...ale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for im...

Page 831: ...CCOB register which is written to with the command global address data and any required command parameters The memory controller must complete the execution of a command before the FCCOB register can...

Page 832: ...he Flash memory D Flash Memory The D Flash memory constitutes the nonvolatile memory store required for EEE Memory space in the D Flash memory not required for EEE can be partitioned to provide nonvol...

Page 833: ...yte sectors for user access Dedicated commands to control access to the D Flash memory over EEE operation Single bit fault correction and double bit fault detection within a word during read operation...

Page 834: ...h command completion and Flash error detection Security mechanism to prevent unauthorized access to the Flash memory 24 1 3 Block Diagram The block diagram of the Flash module is shown in Figure 24 1...

Page 835: ...nterface P Flash sector 0 sector 1 sector 63 8Kx72 16bit internal bus Block 1 XGATE P Flash sector 0 sector 1 sector 63 8Kx72 Block 0 Error Interrupt Request Memory CPU Controller D Flash 16Kx22 Buffe...

Page 836: ...s mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module a...

Page 837: ...phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 24 3 Flash Configuration Field 1 Global Address...

Page 838: ...0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes...

Page 839: ...768 D Flash Memory User and EEE 0x10_8000 0x11_FFFF 98 304 Reserved 0x12_0000 0x12_007F 128 EEE Nonvolatile Information Register EEEIFRON 1 1 1 MMCCTL1 register bit 0x12_0080 0x12_0FFF 3 968 Reserved...

Page 840: ...y Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMON 128 bytes EEE Nonvolatile Information Register EEEIFRON 128 bytes D Flash Memory 32 Kbytes D Flash START 0x10_0000 D Flash User Partit...

Page 841: ...d 0x12_0002 0x12_0003 2 D Flash User Partition duplicate 1 1 Duplicate value used if primary value generates a double bit fault when read during the reset sequence 0x12_0004 0x12_0005 2 Buffer RAM EEE...

Page 842: ...14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 W 0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R...

Page 843: ...7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divid...

Page 844: ...5 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D...

Page 845: ...ved Figure 24 6 Flash Security Register FSEC Table 24 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor ke...

Page 846: ...ex Register FCCOBIX Table 24 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is b...

Page 847: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array re...

Page 848: ...interrupt will be requested whenever the EPVIOLIF flag is set see Section 24 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state error...

Page 849: ...he reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 850: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE partit...

Page 851: ...in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits d...

Page 852: ...he FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning...

Page 853: ...ramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 24 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected S...

Page 854: ...protected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLA...

Page 855: ...f the EPDIS and EPS bits is irrelevant During the reset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Fla...

Page 856: ...e buffer RAM EEE partition is protected from writes 1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased s...

Page 857: ...lemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 24 26 shows the generic Flash command format The high byte of the first word in the...

Page 858: ...double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 24 3 2 4 Once ECC fault information has been...

Page 859: ...1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 24 21 Flash ECC Error Results Low Register FECCRLO Table 24 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8...

Page 860: ...set 24 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 24 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains t...

Page 861: ...5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 24 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0...

Page 862: ...IV register is written the FDIVLD bit is set automatically If the FDIVLD bit is 0 the FCLKDIV register has not been written since the last reset If the FCLKDIV register has not been written any Flash...

Page 863: ...ister to launch command Clear CCIF 0x80 Clear ACCERR FPVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation Read FSTAT register Read FSTAT register no START yes Check CCIF Set F...

Page 864: ...Erase Verify P Flash Section 0x04 Read Once 0x05 Reserved 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C Verif...

Page 865: ...P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior...

Page 866: ...N bits in the EPROT register are set prior to launching the command 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D Flash and P Flash blocks and verifying that all D F...

Page 867: ...ll verify that the entire Flash memory space is erased The CCIF flag will set after the Erase Verify All Blocks operation has completed 24 4 2 2 Erase Verify Block Command The Erase Verify Block comma...

Page 868: ...Flash Section operation has completed Table 24 36 Erase Verify Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch Set if an invalid g...

Page 869: ...ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 24 30 Set if an invalid global address 22 0 is supplied 1 1 As defined by the memory map for FTM2...

Page 870: ...Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 24 30 Set if an invalid phrase index is supplied FPVIOL None MGSTAT1 Set if...

Page 871: ...on of the Program Once command any attempt to read addresses within P Flash block 0 will return invalid data Table 24 42 Program P Flash Command Error Handling Register Error Bit Error Condition FSTAT...

Page 872: ...tially programmed to 0xFFFF_FFFF_FFFF_FFFF the Program Once command will be allowed to execute again on that same phrase FPVIOL None MGSTAT1 Set if any errors have been encountered during the verify o...

Page 873: ...n P Flash block to be erased Table 24 48 Erase P Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available...

Page 874: ...6 is supplied 1 1 As defined by the memory map for FTM256K2 Set if a misaligned phrase address is supplied global address 2 0 000 FPVIOL Set if the selected P Flash sector is protected MGSTAT1 Set if...

Page 875: ...cute the Verify Backdoor Access Key command are aborted set ACCERR until a power down reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 24 4 2 12 Set User...

Page 876: ...fy the Flash block 001 Margin level setting Table 24 56 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin...

Page 877: ...e 24 59 Valid Set Field Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to the erased state 0x0002 User Margin 0 Level...

Page 878: ...D Flash block ERPART 8 maximum number of 256 byte sectors in buffer RAM If ERPART 0 128 DFPART 12 minimum number of 256 byte sectors in the D Flash block required to support EEE If ERPART 0 128 DFPART...

Page 879: ...Memory Controller will verify the selected section of D Flash memory is erased The CCIF flag will set after the Erase Verify D Flash Section operation has completed Table 24 62 Full Partition D Flash...

Page 880: ...rror Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 24 30 Set if an invalid global address 22 0 is supplied Set if a mi...

Page 881: ...f a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to an area in the D Flash EEE partition Set if the requested group of words breaches the end of the D F...

Page 882: ...al address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to the D Flash EEE partition FPVIOL None MGSTAT1 Set if any errors hav...

Page 883: ...artition D Flash Command Section 24 4 2 14 the following reset values are returned DFPART 0x_FFFF ERPART 0x_FFFF ECOUNT 0x_FFFF Dead Sector Count 0x_00 Ready Sector Count 0x_00 Table 24 71 Disable EEP...

Page 884: ...E space to buffer RAM EEE space to support EEE Erase verify the D Flash block and the EEE nonvolatile information register Program DFPART to the EEE nonvolatile information register at global address...

Page 885: ...nerate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault Table 24 76 Partition D Flash Command Error Handling Regist...

Page 886: ...c used for generating the Flash module interrupts is shown in Figure 24 27 Table 24 77 Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global CCR Mask Flash Command Complete CCIF...

Page 887: ...ecurity The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 24 12 During reset the Flash module initializes the...

Page 888: ...ash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in th...

Page 889: ...program the Flash security byte to the unsecured state and reset the MCU 24 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU ope...

Page 890: ...escale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for...

Page 891: ...Changed terminology from word program to Program P Flash in the BDM unsecuring description Section 25 5 2 Added requirement that user not write any Flash module register during execution of commands E...

Page 892: ...written to with a new command CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed The RAM an...

Page 893: ...lest portion of the P Flash memory that can be erased Each P Flash sector contains 1024 bytes Program IFR Nonvolatile information register located in the P Flash block that contains the Device ID Vers...

Page 894: ...sable EEE operation and allow priority access to the D Flash memory Ability to cancel all pending EEE operations and allow priority access to the D Flash memory 25 1 2 4 User Buffer RAM Features Up to...

Page 895: ...rface P Flash sector 0 sector 1 sector 127 16Kx72 16bit internal bus Block 1 XGATE P Flash sector 0 sector 1 sector 127 16Kx72 Block 0 Error Interrupt Request Memory CPU Controller D Flash 16Kx22 Buff...

Page 896: ...mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module ar...

Page 897: ...phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 25 3 Flash Configuration Field 1 Global Address...

Page 898: ...F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected Region 224...

Page 899: ...1 PBLK1 Table 25 6 EEE Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_7FFF 32 768 D Flash Memory User and EEE 0x10_8000 0x11_FFFF 98 304 Reserved 0x12_0000 0x12_007F 128 EEE Nonv...

Page 900: ...y Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMON 256 bytes EEE Nonvolatile Information Register EEEIFRON 128 bytes D Flash Memory 32 Kbytes D Flash START 0x10_0000 D Flash User Partit...

Page 901: ...d 0x12_0002 0x12_0003 2 D Flash User Partition duplicate 1 1 Duplicate value used if primary value generates a double bit fault when read during the reset sequence 0x12_0004 0x12_0005 2 Buffer RAM EEE...

Page 902: ...14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 W 0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R...

Page 903: ...7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divid...

Page 904: ...5 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D...

Page 905: ...ved Figure 25 6 Flash Security Register FSEC Table 25 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor ke...

Page 906: ...ex Register FCCOBIX Table 25 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is b...

Page 907: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array re...

Page 908: ...interrupt will be requested whenever the EPVIOLIF flag is set see Section 25 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state error...

Page 909: ...he reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 910: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE partit...

Page 911: ...in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits d...

Page 912: ...he FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning...

Page 913: ...ramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 25 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected S...

Page 914: ...protected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLA...

Page 915: ...eset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 25 3 as indicated by reset cond...

Page 916: ...1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased state for future enhancements 3 EPDIS Buffer RAM Pro...

Page 917: ...lemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 25 26 shows the generic Flash command format The high byte of the first word in the...

Page 918: ...double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 25 3 2 4 Once ECC fault information has been...

Page 919: ...1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 25 21 Flash ECC Error Results Low Register FECCRLO Table 25 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8...

Page 920: ...set 25 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 25 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains t...

Page 921: ...5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 25 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0...

Page 922: ...CLK of 1 MHz Table 25 9 shows recommended values for the FDIV field based on OSCCLK frequency NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz...

Page 923: ...quired parameters for the Flash command being executed Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register see Section 25 3 2 3 The contents of the FCCOB par...

Page 924: ...Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Completion Check yes CCIF Set to identify specific command parameter to load Wri...

Page 925: ...se Verify P Flash Section 0x04 Read Once 0x05 Load Data Field 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C V...

Page 926: ...sh block 0 that is allowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in...

Page 927: ...the D Flash block 0x0E Set Field Margin Level Specifies a field margin read level for the D Flash block special modes only 0x0F Full Partition D Flash Erase the D Flash block and partition an area of...

Page 928: ...er must clear these bits before starting any command write sequence see Section 25 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bi...

Page 929: ...memory space Table 25 35 Erase Verify Block Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x02 Global address 22 16 of the Flash block to be verified Table 25 36 Erase Verify Block Comma...

Page 930: ...0 will return invalid data 128 Table 25 38 Erase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Dat...

Page 931: ...Program P Flash command the associated Load Data Field command sequence will be cancelled Table 25 40 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2...

Page 932: ...l address 22 0 is supplied Set if a misaligned phrase address is supplied global address 2 0 000 Set if a Load Data Field command sequence is currently active and the selected block has previously bee...

Page 933: ...TAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 25 30 Set if an invalid global address 22 0 is supplied Set if a misaligned phrase address is...

Page 934: ...pleted Table 25 46 Program Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if a Load Data Field command sequence is currently ac...

Page 935: ...fy operation FERSTAT EPVIOLIF Set if any area of the buffer RAM EEE partition is protected Table 25 49 Erase P Flash Block Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x09 Global addres...

Page 936: ...sh Sector Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0A Global address 22 16 to identify P Flash block to be erased 001 Global address 15 0 anywhere within the sector to be erased Re...

Page 937: ...be released If the backdoor keys do not match security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted set ACCERR until a power down reset occurs...

Page 938: ...s currently active Set if an incorrect backdoor key is supplied Set if backdoor key access has not been enabled KEYEN 1 0 10 see Section 25 3 2 2 Set if the backdoor key has mismatched since the last...

Page 939: ...and are defined in Table 25 61 Table 25 59 Set User Margin Level Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if a Load Data Field...

Page 940: ...2 Read margin to the programmed state Table 25 62 Set Field Margin Level Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if a Load D...

Page 941: ...25 7 Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 see Table 25 7 Program ERPART to the EEE nonvolatile information register at global address 0x12...

Page 942: ...TAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 25 30 Set if an invalid DFPART o...

Page 943: ...ld command sequence is currently active Set if command not available in current mode see Table 25 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied glob...

Page 944: ...ot available in current mode see Table 25 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to...

Page 945: ...al address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to the D Flash EEE partition FPVIOL None MGSTAT1 Set if any errors hav...

Page 946: ...n 25 4 2 15 the following reset values are returned DFPART 0x_FFFF ERPART 0x_FFFF ECOUNT 0x_FFFF Dead Sector Count 0x_00 Ready Sector Count 0x_00 Table 25 73 Disable EEPROM Emulation Command FCCOB Req...

Page 947: ...red to support EEE If ERPART 0 128 DFPART ERPART 8 minimum ratio of D Flash EEE space to buffer RAM EEE space to support EEE Erase verify the D Flash block and the EEE nonvolatile information register...

Page 948: ...direct D Flash access DFPART or buffer RAM EEE access ERPART 25 4 3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation...

Page 949: ...c used for generating the Flash module interrupts is shown in Figure 25 27 Table 25 79 Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global CCR Mask Flash Command Complete CCIF...

Page 950: ...ecurity The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 25 12 During reset the Flash module initializes the...

Page 951: ...ash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in th...

Page 952: ...program the Flash security byte to the unsecured state and reset the MCU 25 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU ope...

Page 953: ...3 1 26 958 Updated Command Error Handling tables based on parent child relationship with FTM512K3 Corrected Error Handling table for Full Partition D Flash Partition D Flash and EEPROM Emulation Quer...

Page 954: ...plete the execution of a command before the FCCOB register can be written to with a new command CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programmin...

Page 955: ...ry The P Flash memory constitutes the main nonvolatile memory store for applications P Flash Sector The P Flash sector is the smallest portion of the P Flash memory that can be erased Each P Flash sec...

Page 956: ...Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation and allow priority access to the D Flash memory Abi...

Page 957: ...32Kx72 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 P Flash sector 0 sector 1 sector 127 16Kx72 16bit internal bus Block 1 XGATE 16Kx72 16Kx72 Error Interrupt Request CPU Memory Controlle...

Page 958: ...mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module ar...

Page 959: ...phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 26 3 Flash Configuration Field 1 Global Address...

Page 960: ...0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0...

Page 961: ...768 D Flash Memory User and EEE 0x10_8000 0x11_FFFF 98 304 Reserved 0x12_0000 0x12_007F 128 EEE Nonvolatile Information Register EEEIFRON 1 1 1 MMCCTL1 register bit 0x12_0080 0x12_0FFF 3 968 Reserved...

Page 962: ...y Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMON 256 bytes EEE Nonvolatile Information Register EEEIFRON 128 bytes D Flash Memory 32 Kbytes D Flash START 0x10_0000 D Flash User Partit...

Page 963: ...d 0x12_0002 0x12_0003 2 D Flash User Partition duplicate 1 1 Duplicate value used if primary value generates a double bit fault when read during the reset sequence 0x12_0004 0x12_0005 2 Buffer RAM EEE...

Page 964: ...14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 W 0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R...

Page 965: ...7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divid...

Page 966: ...5 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D...

Page 967: ...ved Figure 26 6 Flash Security Register FSEC Table 26 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor ke...

Page 968: ...ex Register FCCOBIX Table 26 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is b...

Page 969: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array re...

Page 970: ...interrupt will be requested whenever the EPVIOLIF flag is set see Section 26 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state error...

Page 971: ...he reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 972: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE partit...

Page 973: ...in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits d...

Page 974: ...he FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning...

Page 975: ...ramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 26 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected S...

Page 976: ...protected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLA...

Page 977: ...f the EPDIS and EPS bits is irrelevant During the reset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Fla...

Page 978: ...e buffer RAM EEE partition is protected from writes 1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased s...

Page 979: ...lemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 26 26 shows the generic Flash command format The high byte of the first word in the...

Page 980: ...double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 26 3 2 4 Once ECC fault information has been...

Page 981: ...1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 26 21 Flash ECC Error Results Low Register FECCRLO Table 26 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8...

Page 982: ...set 26 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 26 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains t...

Page 983: ...5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 26 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0...

Page 984: ...FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 26 4 1 2 Command Writ...

Page 985: ...ead FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Compl...

Page 986: ...se Verify P Flash Section 0x04 Read Once 0x05 Load Data Field 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C V...

Page 987: ...sh block 0 that is allowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in...

Page 988: ...the D Flash block 0x0E Set Field Margin Level Specifies a field margin read level for the D Flash block special modes only 0x0F Full Partition D Flash Erase the D Flash block and partition an area of...

Page 989: ...ts before starting any command write sequence see Section 26 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word...

Page 990: ...Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x02 Global address 22 16 of the Flash block to be verified Table 26 36 Erase Verify Block Command Error Handling Register Error Bit Error Co...

Page 991: ...ase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active...

Page 992: ...Program P Flash command the associated Load Data Field command sequence will be cancelled Table 26 40 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2...

Page 993: ...ied 1 1 As defined by the memory map for FTM512K3 Set if a misaligned phrase address is supplied global address 2 0 000 Set if a Load Data Field command sequence is currently active and the selected b...

Page 994: ...ected block has previously been selected in the same command sequence Set if a Load Data Field command sequence is currently active and global address 17 0 does not match that previously supplied in t...

Page 995: ...mmand any attempt to read addresses within P Flash block 0 will return invalid data Table 26 45 Program Once Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x07 Not Required 001 Program On...

Page 996: ...P Flash Block operation has completed Table 26 47 Erase All Blocks Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x08 Not required Table 26 48 Erase All Blocks Command Error Handling Regi...

Page 997: ...f an invalid global address 22 16 is supplied 1 1 As defined by the memory map for FTM512K3 FPVIOL Set if an area of the selected P Flash block is protected MGSTAT1 Set if any errors have been encount...

Page 998: ...d global address 22 16 is supplied 1 1 As defined by the memory map for FTM512K3 Set if a misaligned phrase address is supplied global address 2 0 000 FPVIOL Set if the selected P Flash sector is prot...

Page 999: ...s not released and all future attempts to execute the Verify Backdoor Access Key command are aborted set ACCERR until a power down reset occurs The CCIF flag is set after the Verify Backdoor Access Ke...

Page 1000: ...Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to the erased state 0x0002 User Margin 0 Level 2 2 Read margin to the...

Page 1001: ...the field margin level for the targeted block and then set the CCIF flag Valid margin level settings for the Set Field Margin Level command are defined in Table 26 61 Table 26 60 Set Field Margin Leve...

Page 1002: ...Margin Level Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if a Load Data Field command sequence is currently active Set if comman...

Page 1003: ...26 7 Program a duplicate DFPART to the EEE nonvolatile information register at global address 0x12_0002 see Table 26 7 Program ERPART to the EEE nonvolatile information register at global address 0x1...

Page 1004: ...STAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 26 30 Set if an invalid DFPART...

Page 1005: ...ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 26 30 Set if an invalid global addr...

Page 1006: ...l address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to an area in the D Flash EEE partition Set if the requested group of w...

Page 1007: ...bal address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to the D Flash EEE partition FPVIOL None MGSTAT1 Set if any errors ha...

Page 1008: ...on 26 4 2 15 the following reset values are returned DFPART 0x_FFFF ERPART 0x_FFFF ECOUNT 0x_FFFF Dead Sector Count 0x_00 Ready Sector Count 0x_00 Table 26 73 Disable EEPROM Emulation Command FCCOB Re...

Page 1009: ...um ratio of D Flash EEE space to buffer RAM EEE space to support EEE Erase verify the D Flash block and the EEE nonvolatile information register Program DFPART to the EEE nonvolatile information regis...

Page 1010: ...PART 26 4 3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operation has detected an EEE error or an ECC fault Table 26 78 P...

Page 1011: ...c used for generating the Flash module interrupts is shown in Figure 26 27 Table 26 79 Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global CCR Mask Flash Command Complete CCIF...

Page 1012: ...Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 26 12 During reset the Flash module initializes th...

Page 1013: ...ash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in th...

Page 1014: ...program the Flash security byte to the unsecured state and reset the MCU 26 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU op...

Page 1015: ...ov 2007 27 5 2 27 1075 27 4 2 27 1050 27 4 2 27 1050 Changed terminology from word program to Program P Flash in the BDM unsecuring description Section 27 5 2 Added requirement that user not write any...

Page 1016: ...mplete the execution of a command before the FCCOB register can be written to with a new command CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programmi...

Page 1017: ...fault detection within the phrase P Flash Memory The P Flash memory constitutes the main nonvolatile memory store for applications P Flash Sector The P Flash sector is the smallest portion of the P Fl...

Page 1018: ...E data from D Flash memory to buffer RAM on reset Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation a...

Page 1019: ...ector 127 sector 0 sector 1 sector 127 P Flash sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16Kx72 16Kx72 16bit internal bus P Flash Block 1S Block 1N XGATE 16Kx72 16Kx72 Error Interrupt...

Page 1020: ...s mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module a...

Page 1021: ...phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 27 3 Flash Configuration Field 1 Global Address...

Page 1022: ...F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected...

Page 1023: ...1 PBLK1S Table 27 6 EEE Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_7FFF 32 768 D Flash Memory User and EEE 0x10_8000 0x11_FFFF 98 304 Reserved 0x12_0000 0x12_007F 128 EEE Non...

Page 1024: ...ry Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMON 256 bytes EEE Nonvolatile Information Register EEEIFRON 128 bytes D Flash Memory 32 Kbytes D Flash START 0x10_0000 D Flash User Parti...

Page 1025: ...d 0x12_0002 0x12_0003 2 D Flash User Partition duplicate 1 1 Duplicate value used if primary value generates a double bit fault when read during the reset sequence 0x12_0004 0x12_0005 2 Buffer RAM EEE...

Page 1026: ...G14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 W 0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO...

Page 1027: ...7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divid...

Page 1028: ...45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D...

Page 1029: ...ved Figure 27 6 Flash Security Register FSEC Table 27 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor ke...

Page 1030: ...ex Register FCCOBIX Table 27 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is b...

Page 1031: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array re...

Page 1032: ...n interrupt will be requested whenever the EPVIOLIF flag is set see Section 27 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state error...

Page 1033: ...he reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 1034: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE partit...

Page 1035: ...in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits...

Page 1036: ...the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning...

Page 1037: ...ramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 27 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected S...

Page 1038: ...nprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FL...

Page 1039: ...eset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 27 3 as indicated by reset cond...

Page 1040: ...1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased state for future enhancements 3 EPDIS Buffer RAM Pro...

Page 1041: ...plemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 27 26 shows the generic Flash command format The high byte of the first word in the...

Page 1042: ...le bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 27 3 2 4 Once ECC fault information has been stor...

Page 1043: ...1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 27 21 Flash ECC Error Results Low Register FECCRLO Table 27 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8...

Page 1044: ...e set 27 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 27 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains...

Page 1045: ...6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 27 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0...

Page 1046: ...FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 27 4 1 2 Command Wri...

Page 1047: ...Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Comp...

Page 1048: ...se Verify P Flash Section 0x04 Read Once 0x05 Load Data Field 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C V...

Page 1049: ...owed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register an...

Page 1050: ...its in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D Fl...

Page 1051: ...erify Block command the Memory Controller will verify that the selected P Flash or D Flash block is erased The CCIF flag will set after the Erase Verify Block operation has completed Table 27 33 Erase...

Page 1052: ...se Verify Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch Set if a Load Data Field command sequence is currently active Set if an i...

Page 1053: ...r Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 27 30 Set if an in...

Page 1054: ...Program P Flash command the associated Load Data Field command sequence will be cancelled Table 27 40 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2...

Page 1055: ...al address 22 0 is supplied Set if a misaligned phrase address is supplied global address 2 0 000 Set if a Load Data Field command sequence is currently active and the selected block has previously be...

Page 1056: ...STAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 27 30 Set if an invalid global address 22 0 is supplied Set if a misaligned phrase address is...

Page 1057: ...pleted Table 27 46 Program Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if a Load Data Field command sequence is currently ac...

Page 1058: ...fy operation FERSTAT EPVIOLIF Set if any area of the buffer RAM EEE partition is protected Table 27 49 Erase P Flash Block Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x09 Global addres...

Page 1059: ...ash Sector Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0A Global address 22 16 to identify P Flash block to be erased 001 Global address 15 0 anywhere within the sector to be erased R...

Page 1060: ...be released If the backdoor keys do not match security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted set ACCERR until a power down reset occurs...

Page 1061: ...is currently active Set if an incorrect backdoor key is supplied Set if backdoor key access has not been enabled KEYEN 1 0 10 see Section 27 3 2 2 Set if the backdoor key has mismatched since the last...

Page 1062: ...mand are defined in Table 27 61 Table 27 59 Set User Margin Level Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if a Load Data Fiel...

Page 1063: ...56 bytes per sector 0x0002 User Margin 0 Level 2 0x0003 Field Margin 1 Level1 0x0004 Field Margin 0 Level2 1 Read margin to the erased state 2 Read margin to the programmed state Table 27 62 Set Field...

Page 1064: ...he EEE nonvolatile information register at global address 0x12_0004 see Table 27 7 Program a duplicate ERPART to the EEE nonvolatile information register at global address 0x12_0006 see Table 27 7 The...

Page 1065: ...STAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 27 30 Set if an invalid DFPART...

Page 1066: ...eld command sequence is currently active Set if command not available in current mode see Table 27 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied glo...

Page 1067: ...not available in current mode see Table 27 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to...

Page 1068: ...bal address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to the D Flash EEE partition FPVIOL None MGSTAT1 Set if any errors ha...

Page 1069: ...on 27 4 2 15 the following reset values are returned DFPART 0x_FFFF ERPART 0x_FFFF ECOUNT 0x_FFFF Dead Sector Count 0x_00 Ready Sector Count 0x_00 Table 27 73 Disable EEPROM Emulation Command FCCOB Re...

Page 1070: ...ired to support EEE If ERPART 0 128 DFPART ERPART 8 minimum ratio of D Flash EEE space to buffer RAM EEE space to support EEE Erase verify the D Flash block and the EEE nonvolatile information registe...

Page 1071: ...direct D Flash access DFPART or buffer RAM EEE access ERPART 27 4 3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operatio...

Page 1072: ...c used for generating the Flash module interrupts is shown in Figure 27 27 Table 27 79 Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global CCR Mask Flash Command Complete CCIF...

Page 1073: ...Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 27 12 During reset the Flash module initializes th...

Page 1074: ...ash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in th...

Page 1075: ...program the Flash security byte to the unsecured state and reset the MCU 27 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU op...

Page 1076: ...escale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for...

Page 1077: ...3 1 28 1082 Updated Command Error Handling tables based on parent child relationship with FTM1024K5 Corrected Error Handling table for Full Partition D Flash Partition D Flash and EEPROM Emulation Qu...

Page 1078: ...mplete the execution of a command before the FCCOB register can be written to with a new command CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programmi...

Page 1079: ...ault detection within the phrase P Flash Memory The P Flash memory constitutes the main nonvolatile memory store for applications P Flash Sector The P Flash sector is the smallest portion of the P Fla...

Page 1080: ...E data from D Flash memory to buffer RAM on reset Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation a...

Page 1081: ...sector 1 sector 127 sector 0 sector 1 sector 127 P Flash sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16Kx72 16Kx72 16bit internal bus P Flash Block 1S Block 1N XGATE 16Kx72 16Kx72 16Kx72...

Page 1082: ...is mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module...

Page 1083: ...e addresses 2 0x7FF08 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 28...

Page 1084: ...F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected...

Page 1085: ...FF 512 XBUS0 PBLK2S 0x40_0A00 0x40_0BFF 512 Unimplemented Table 28 6 EEE Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_7FFF 32 768 D Flash Memory User and EEE 0x10_8000 0x11_FFF...

Page 1086: ...2_1000 Memory Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMON 256 bytes EEE Nonvolatile Information Register EEEIFRON 128 bytes D Flash Memory 32 Kbytes D Flash START 0x10_0000 D Flash...

Page 1087: ...d 0x12_0002 0x12_0003 2 D Flash User Partition duplicate 1 1 Duplicate value used if primary value generates a double bit fault when read during the reset sequence 0x12_0004 0x12_0005 2 Buffer RAM EEE...

Page 1088: ...G14 ETAG13 ETAG12 ETAG11 ETAG10 ETAG9 ETAG8 W 0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO...

Page 1089: ...7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divid...

Page 1090: ...45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D...

Page 1091: ...ved Figure 28 6 Flash Security Register FSEC Table 28 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor ke...

Page 1092: ...ex Register FCCOBIX Table 28 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is b...

Page 1093: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array re...

Page 1094: ...n interrupt will be requested whenever the EPVIOLIF flag is set see Section 28 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state error...

Page 1095: ...he reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 1096: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE partit...

Page 1097: ...in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits...

Page 1098: ...the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning...

Page 1099: ...ramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 28 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected S...

Page 1100: ...nprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FL...

Page 1101: ...eset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 28 3 as indicated by reset cond...

Page 1102: ...1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased state for future enhancements 3 EPDIS Buffer RAM Pro...

Page 1103: ...plemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 28 26 shows the generic Flash command format The high byte of the first word in the...

Page 1104: ...double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 28 3 2 4 Once ECC fault information has been...

Page 1105: ...1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 28 21 Flash ECC Error Results Low Register FECCRLO Table 28 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8...

Page 1106: ...e set 28 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 28 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains...

Page 1107: ...6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 28 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0...

Page 1108: ...FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 28 4 1 2 Command Wri...

Page 1109: ...Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Comp...

Page 1110: ...se Verify P Flash Section 0x04 Read Once 0x05 Load Data Field 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C V...

Page 1111: ...owed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register an...

Page 1112: ...its in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D Fl...

Page 1113: ...Memory Controller will verify that the selected P Flash or D Flash block is erased The CCIF flag will set after the Erase Verify Block operation has completed Table 28 33 Erase Verify All Blocks Comm...

Page 1114: ...Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch Set if a Load Data Field command sequence is currently active Set if an invalid global address 22 16 is supplied 1 1 As...

Page 1115: ...at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 28 30 Set if an invalid global address 22 0 is supplied 1 1 As d...

Page 1116: ...Program P Flash command the associated Load Data Field command sequence will be cancelled Table 28 40 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2...

Page 1117: ...et if a Load Data Field command sequence is currently active and the selected block has previously been selected in the same command sequence Set if a Load Data Field command sequence is currently act...

Page 1118: ...3 program value Table 28 44 Program P Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode...

Page 1119: ...ommand any attempt to read addresses within P Flash block 0 will return invalid data Table 28 45 Program Once Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x07 Not Required 001 Program O...

Page 1120: ...P Flash Block operation has completed Table 28 47 Erase All Blocks Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x08 Not required Table 28 48 Erase All Blocks Command Error Handling Regi...

Page 1121: ...f an invalid global address 22 16 is supplied 1 1 As defined by the memory map for FTM1024K5 FPVIOL Set if an area of the selected P Flash block is protected MGSTAT1 Set if any errors have been encoun...

Page 1122: ...t mode see Table 28 30 Set if an invalid global address 22 16 is supplied 1 1 As defined by the memory map for FTM1024K5 Set if a misaligned phrase address is supplied global address 2 0 000 FPVIOL Se...

Page 1123: ...Key command are aborted set ACCERR until a power down reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed FERSTAT EPVIOLIF Set if any area of the buffer RAM...

Page 1124: ...in Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to the erased state 0x0002 User Margin 0 Level 2 2 Read margin to the progr...

Page 1125: ...margin level settings for the Set Field Margin Level command are defined in Table 28 61 FERSTAT EPVIOLIF None 1 As defined by the memory map for FTM1024K5 Table 28 60 Set Field Margin Level Command FC...

Page 1126: ...partition within the buffer RAM for EEE use ERPART Validate the DFPART and ERPART values provided DFPART 128 maximum number of 256 byte sectors in D Flash block Table 28 62 Set Field Margin Level Comm...

Page 1127: ...Flash command a second time will result in the previous partition values and the entire D Flash memory being erased The data value written corresponds to the number of 256 byte sectors allocated for...

Page 1128: ...to be verified Table 28 66 Erase Verify D Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command...

Page 1129: ...at command launch Set if CCOBIX 2 0 101 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 28 30 Set if an invalid...

Page 1130: ...ctor size Table 28 70 Erase D Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if a Load Data Field command sequence is c...

Page 1131: ...d command sequence is currently active Set if Full Partition D Flash or Partition D Flash command not previously run FPVIOL None MGSTAT1 None MGSTAT0 None FERSTAT EPVIOLIF None Table 28 73 Disable EEP...

Page 1132: ...ash command 010 Return ERPART 011 Return ECOUNT 1 100 Return Dead Sector Count Return Ready Sector Count 1 Indicates sector erase count Table 28 76 EEPROM Emulation Query Command Error Handling Regist...

Page 1133: ...e information register at global address 0x12_0006 see Table 28 7 The D Flash user partition will start at global address 0x10_0000 The buffer RAM EEE partition will end at global address 0x13_FFFF Af...

Page 1134: ...ash Status Register FSTAT and Section 28 3 2 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 28 27 Table 28 79 Flash Interrupt Source...

Page 1135: ...Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 28 12 During reset the Flash module initializes th...

Page 1136: ...ash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in th...

Page 1137: ...program the Flash security byte to the unsecured state and reset the MCU 28 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU op...

Page 1138: ...escale Semiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for...

Page 1139: ...ection 29 5 2 Section 29 4 2 Section 29 4 2 8 Changed terminology from word program to Program P Flash in the BDM unsecuring description Section 29 5 2 Added requirement that user not write any Flash...

Page 1140: ...omplete the execution of a command before the FCCOB register can be written to with a new command CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programm...

Page 1141: ...ault detection within the phrase P Flash Memory The P Flash memory constitutes the main nonvolatile memory store for applications P Flash Sector The P Flash sector is the smallest portion of the P Fla...

Page 1142: ...EE data from D Flash memory to buffer RAM on reset Ability to monitor the number of outstanding EEE related buffer RAM words left to be programmed into D Flash memory Ability to disable EEE operation...

Page 1143: ...or 127 sector 0 sector 1 sector 127 16Kx72 16Kx72 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 P Flash sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16Kx72 16Kx72 16bit intern...

Page 1144: ...on is mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash modu...

Page 1145: ...te addresses 2 0x7FF08 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF Table 29...

Page 1146: ..._F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected...

Page 1147: ...Accessibility Global Address PGMIFRON Size Bytes Accessed From 0x40_0000 0x40_01FF 512 XBUS0 PBLK0S 1 1 Refer to Table 29 4 for more details 0x40_0200 0x40_03FF 512 Unimplemented 0x40_0400 0x40_05FF 5...

Page 1148: ...2_1000 0x12_1EFF 3 840 Reserved 0x12_1F00 0x12_1FFF 256 EEE Tag RAM TMGRAMON1 1 0x12_2000 0x12_3BFF 7 168 Reserved 0x12_3C00 0x12_3FFF 1 024 Memory Controller Scratch RAM TMGRAMON1 1 0x12_4000 0x12_DF...

Page 1149: ...20 384 448 512 bytes Buffer RAM 4 Kbytes 0x13_FF40 0x13_FF00 0x13_FEC0 0x13_FE80 0x13_FE40 0x13_FE00 0x12_FFFF 0x12_4000 0x12_1000 Memory Controller Scratch RAM TMGRAMON 1024 bytes EEE Tag RAM TMGRAMO...

Page 1150: ...12_0004 0x12_0005 2 Buffer RAM EEE Partition ERPART Refer to Section 29 4 2 15 Full Partition D Flash Command 0x12_0006 0x12_0007 2 Buffer RAM EEE Partition duplicate1 0x12_0008 0x12_007F 120 Reserved...

Page 1151: ...0x000D ETAGLO R ETAG7 ETAG6 ETAG5 ETAG4 ETAG3 ETAG2 ETAG1 ETAG0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 EC...

Page 1152: ...riptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must...

Page 1153: ...45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2...

Page 1154: ...rved Figure 29 6 Flash Security Register FSEC Table 29 10 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor k...

Page 1155: ...dex Register FCCOBIX Table 29 13 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is...

Page 1156: ...bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array r...

Page 1157: ...An interrupt will be requested whenever the EPVIOLIF flag is set see Section 29 3 2 8 3 ERSVIE1 EEE Error Type 1 Interrupt Enable The ERSVIE1 bit controls interrupt generation when a change state erro...

Page 1158: ...the reset sequence While ACCERR is set the CCIF flag cannot be cleared to launch a command The ACCERR bit is cleared by writing a 1 to ACCERR Writing a 0 to the ACCERR bit has no effect on ACCERR 0 No...

Page 1159: ...on the D Flash EEE partition 4 EPVIOLIF EEE Protection Violation Interrupt Flag The setting of the EPVIOLIF flag indicates an attempt was made to write to a protected area of the buffer RAM EEE parti...

Page 1160: ...d in the same P Flash block are protected 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits...

Page 1161: ...the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginnin...

Page 1162: ...gramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 29 22 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected...

Page 1163: ...Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START F...

Page 1164: ...reset sequence the EPROT register is loaded from the EEE protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 29 3 as indicated by reset con...

Page 1165: ...s 1 Unprotected buffer RAM EEE partition areas are enabled for writes 6 4 RNV 6 4 Reserved Nonvolatile Bits The RNV bits should remain in the erased state for future enhancements 3 EPDIS Buffer RAM Pr...

Page 1166: ...mplemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 29 26 shows the generic Flash command format The high byte of the first word in th...

Page 1167: ...d double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 29 3 2 4 Once ECC fault information has bee...

Page 1168: ...2 1 0 R ECCR 7 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 29 21 Flash ECC Error Results Low Register FECCRLO Table 29 27 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15...

Page 1169: ...be set 29 3 2 15 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing Table 29 28 FECCR Index 000 Bit Descriptions Field Description 15 8 PAR 7 0 ECC Parity Bits Contains...

Page 1170: ...6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 29 23 Flash Reserved0 Register FRSV0 Offset Module Base 0x0012 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0...

Page 1171: ...e FCLKDIV register has not been written any Flash program or erase command loaded during a command write sequence will not execute and the ACCERR bit in the FSTAT register will set 29 4 1 2 Command Wr...

Page 1172: ...Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Com...

Page 1173: ...ase Verify P Flash Section 0x04 Read Once 0x05 Load Data Field 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks 0x09 Erase P Flash Block 0x0A Erase P Flash Sector 0x0B Unsecure Flash 0x0C...

Page 1174: ...lowed to be programmed only once 0x08 Erase All Blocks Erase all P Flash and D Flash blocks An erase of all Flash blocks is only possible when the FPLDIS FPHDIS and FPOPEN bits in the FPROT register a...

Page 1175: ...bits in the FPROT register and the EPDIS and EPOPEN bits in the EPROT register are set prior to launching the command 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all D F...

Page 1176: ...Verify Block command the Memory Controller will verify that the selected P Flash or D Flash block is erased The CCIF flag will set after the Erase Verify Block operation has completed Table 29 33 Eras...

Page 1177: ...ase Verify Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch Set if a Load Data Field command sequence is currently active Set if an...

Page 1178: ...or Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if a Load Data Field command sequence is currently active Set if command not available in current mode see Table 29 30 Set if an i...

Page 1179: ...r Program P Flash command the associated Load Data Field command sequence will be cancelled Table 29 40 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2...

Page 1180: ...bal address 22 0 is supplied Set if a misaligned phrase address is supplied global address 2 0 000 Set if a Load Data Field command sequence is currently active and the selected block has previously b...

Page 1181: ...FSTAT ACCERR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 29 30 Set if an invalid global address 22 0 is supplied Set if a misaligned phrase address i...

Page 1182: ...see Table 29 30 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed 1 1 If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF the Pr...

Page 1183: ...ill set after the Erase P Flash Block operation has completed Table 29 47 Erase All Blocks Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x08 Not required Table 29 48 Erase All Blocks Com...

Page 1184: ...the verify operation FERSTAT EPVIOLIF None Table 29 51 Erase P Flash Sector Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0A Global address 22 16 to identify P Flash block to be erased...

Page 1185: ...e Verify Backdoor Access Key command releases security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 29 3 FERSTAT EPVIOLIF None Table...

Page 1186: ...roller to set the margin level for future read operations of a specific P Flash or D Flash block Table 29 55 Verify Backdoor Access Key Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0C...

Page 1187: ...block 001 Margin level setting Table 29 58 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to the erased...

Page 1188: ...tion 0x0000 Return to Normal Level 0x0001 User Margin 1 Level 1 1 Read margin to the erased state 0x0002 User Margin 0 Level 2 2 Read margin to the programmed state 0x0003 Field Margin 1 Level1 0x0004...

Page 1189: ...ck required to support EEE If ERPART 0 128 DFPART ERPART 8 minimum ratio of D Flash EEE space to buffer RAM EEE space to support EEE Erase the D Flash block and the EEE nonvolatile information registe...

Page 1190: ...e Erase Verify D Flash Section operation has completed Table 29 64 Full Partition D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch...

Page 1191: ...ield command sequence is currently active Set if command not available in current mode see Table 29 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied gl...

Page 1192: ...not available in current mode see Table 29 30 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points t...

Page 1193: ...obal address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the global address 22 0 points to the D Flash EEE partition FPVIOL None MGSTAT1 Set if any errors h...

Page 1194: ...ion 29 4 2 15 the following reset values are returned DFPART 0x_FFFF ERPART 0x_FFFF ECOUNT 0x_FFFF Dead Sector Count 0x_00 Ready Sector Count 0x_00 Table 29 73 Disable EEPROM Emulation Command FCCOB R...

Page 1195: ...uired to support EEE If ERPART 0 128 DFPART ERPART 8 minimum ratio of D Flash EEE space to buffer RAM EEE space to support EEE Erase verify the D Flash block and the EEE nonvolatile information regist...

Page 1196: ...r direct D Flash access DFPART or buffer RAM EEE access ERPART 29 4 3 Interrupts The Flash module can generate an interrupt when a Flash command operation has completed or when a Flash command operati...

Page 1197: ...ic used for generating the Flash module interrupts is shown in Figure 29 27 Table 29 79 Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global CCR Mask Flash Command Complete CCIF...

Page 1198: ...Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 29 12 During reset the Flash module initializes t...

Page 1199: ...lash memory must have a method of receiving the backdoor keys from an external stimulus This external stimulus would typically be through one of the on chip serial ports If the KEYEN 1 0 bits are in t...

Page 1200: ...o program the Flash security byte to the unsecured state and reset the MCU 29 5 3 Mode and Security Effects on Flash Command Availability The availability of Flash module commands depends on the MCU o...

Page 1201: ...bles where appropriate P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design characterization by measuring a statistically...

Page 1202: ...either VDDA VDDR and VDDX VSS35 is used for either VSSA and VSSX unless otherwise noted IDD35 denotes the sum of the currents flowing into the VDDA and VDDR pins The Run mode current in the VDDX domai...

Page 1203: ...This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ra...

Page 1204: ...pply The absolute maximum ratings apply when the device is powered from an external source VDD 0 3 2 16 V 3 PLL supply voltage2 VDDPLL 0 3 2 16 V 4 NVM supply voltage2 VDDF 0 3 3 6 V 5 Voltage differe...

Page 1205: ...Minimum input voltage limit 2 5 V Maximum input voltage limit 7 5 V Table A 3 ESD and Latch Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model HBM VHBM 2000 V 2 C Char...

Page 1206: ...to Table A 15 Voltage difference VSS1 VSS2 VSS3 VSSPLL to VSSX VSS 0 1 0 0 1 V Digital logic supply voltage1 VDD 1 72 1 8 1 98 V PLL supply voltage VDDPLL 1 72 1 8 1 98 V Oscillator2 Loop Controlled...

Page 1207: ...and disabled must be considered 1 Internal voltage regulator disabled 2 Internal voltage regulator enabled T J T A P D JA T J Junction Temperature C T A Ambient Temperature C P D Total Chip Power Diss...

Page 1208: ...ermal resistance JA was simulated to be equivalent to the JEDEC specification JESD51 7 in a horizontal configuration in natural convection JA 32 C W 13 D Junction to Board LQFP112 JB 22 C W 14 D Junct...

Page 1209: ...T 2 C W QFP80 11a D Thermal resistance single sided PCB natural convection JA 50 C W 11b D Thermal resistance single sided PCB 200 ft min JA 40 C W 12a D Thermal resistance double sided PCB with 2 int...

Page 1210: ...nput leakage current pins in high impedance input mode Vin VDD35 or VSS35 40 C 27 C 70 C 85 C 100 C 105 C 110 C 120 C 125 C 130 C 150 C I in 1 1 8 14 26 32 40 60 74 92 240 nA 5 C Output high voltage p...

Page 1211: ...WXIRQ 4 tosc 1 Maximum leakage current occurs at maximum operating temperature 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in stop or pseudo stop mode Table A...

Page 1212: ...60 74 92 240 nA 5 C Output high voltage pins in output mode Partial drive IOH 2 mA V OH VDD35 0 8 V 6 P Output high voltage pins in output mode Full drive IOH 10 mA VOH VDD35 0 8 V 7 C Output low volt...

Page 1213: ...on A 1 4 Current Injection for more details 3 Parameter only applies in stop or pseudo stop mode Table A 8 5V I O Characteristics Conditions are 4 5 V VDD35 5 5 V temperature from 40 C to 150 C unless...

Page 1214: ...chip currents and add the currents due to the external loads Since the DBG and BDM modules are typically not used in the end application the supply current values for these modules is not specified An...

Page 1215: ...igured to operate at its maximum specified frequency and to continuously convert voltages on all input channels in sequence PIT PIT is enabled Micro timer register 0 and 1 loaded with 0F and timer reg...

Page 1216: ...12 76 mA 2 T XGATE 24 20 3 T Each MSCAN 1 05 4 T Each SPI 0 22 5 T Each SCI 0 28 6 T Each IIC 0 40 7 T PWM 0 55 8 T ECT 1 16 9 T Each ATD 0 82 10 T PIT 0 61 11 T RTI 0 17 12 T Overhead 35 56 Because...

Page 1217: ...35 21 mA 4 T T T Peripheral Set3 fosc 4MHz fbus 50MHz fosc 4MHz fbus 20MHz fosc 4MHz fbus 8MHz 3 The following peripherals are on ATD0 ATD1 ECT IIC1 PWM SPI0 SPI2 SCI0 SCI7 62 34 21 mA 5 T T T Periph...

Page 1218: ...enabled PLL off LCP mode 11 C C C C C C 27 C 70 C 85 C 105 C 125 C 150 C IDDPS 205 275 325 475 810 1575 A Stop Current 12 C P C C C P C P P 40 C 27 C 70 C 85 C 105 C 110 C 125 C 130 C 150 C IDDS 20 30...

Page 1219: ...DDX to VDDA VDDX 2 35 0 0 1 V 3 D Voltage difference VSSX to VSSA VSSX 0 1 0 0 1 V 4 C Differential reference voltage1 1 Full accuracy is not guaranteed when differential voltage is less than 4 50 V V...

Page 1220: ...than worst case or leakage induced error is acceptable larger values of source resistance of up to 10Kohm are allowed A 2 2 3 Source Capacitance When sampling an additional internal capacitor is swit...

Page 1221: ...he sum of all DNLs Table A 16 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Max input source resistance1 1 Refer to A...

Page 1222: ...4 7 6 50 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 5055 10 Bit Absolute E...

Page 1223: ...0 5 counts 11 C Integral Nonlinearity 8 Bit INL 1 0 5 1 counts 12 C Absolute Error3 8 Bit AE 1 5 1 1 5 counts Conditions are shown in Table A 4 unless otherwise noted VREF VRH VRL 3 3V fATDCLK 8 3MHz...

Page 1224: ...m a blank check is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per phrase to verify plus a setup of the command Assuming that no non...

Page 1225: ...ulated using the following equation The maximum phrase programming time can be calculated using the following equation A 3 1 7 P Flash Program Once FCMD 0x07 The maximum P Flash Program Once time is g...

Page 1226: ...aximum verify backdoor access key time is given by A 3 1 13 Set User Margin Level FCMD 0x0D The maximum set user margin level time is given by A 3 1 14 Set Field Margin Level FCMD 0x0E The maximum set...

Page 1227: ...and BC 1 if a boundary is crossed The maximum programming time can be calculated using the following equation A 3 1 18 Erase D Flash Sector FCMD 0x12 Typical D Flash sector erase times are those expec...

Page 1228: ...ximum possible is 33 2048 EEE RAM words 63 32 5 although this is a highly unlikely scenario The impact of a worst case brownout recovery scenario is denoted by BWN 2 for non brownout situations BWN 0...

Page 1229: ...1 22 EEE Query FCMD 0x15 Maximum time for the EEE query command is given by A 3 1 23 Partition D Flash FCMD 0x20 The maximum time for partitioning the D flash ERPART 16 DFPART 0 is given by t 32364 1...

Page 1230: ...using D LOAD on 2 blocks tbwpgm2 185 202 s 6 P P Flash sector erase time tera 20 21 ms 7 P Erase All Blocks Mass erase time tmass 101 102 ms 7a D Unsecure Flash tuns 101 102 ms 8 D P Flash erase verif...

Page 1231: ...temperature of TJavg 85 C3 after up to 50 000 program erase cycles tDNVMRET 5 1002 Years 5 C Data retention at an average junction temperature of TJavg 85 C3 after less than 10 000 program erase cycl...

Page 1232: ...le over the lifetime of a consumer industrial or automotive application 4 This represents the number of writes of updated data words to the EEE_RAM partition Minimum specification endurance and data r...

Page 1233: ...2 Low Voltage InterruptDeassert Level 2 Monitors VDDA active only in Full Performance Mode Indicates I O ADC performance degradation due to low supply voltage VLVIA VLVID 4 04 4 19 4 23 4 38 4 40 4 4...

Page 1234: ...MC9S12XE Family Chip Power up and Voltage Drops not scaled Table A 22 Sailfish Required Capacitive Loads Num Characteristic Symbol Min Recommended Max Unit 1 VDD VDDF external capacitive load CDDext...

Page 1235: ...device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after a time tCQOUT no valid oscillation is detected the MCU will start using the i...

Page 1236: ...ry Out of stop the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system If the MCU is woken up by an interrupt...

Page 1237: ...tUPOSC 2 10 ms 4d C Oscillator start up time full swing Pierce 16MHz 3 tUPOSC 1 5 ms 4e C Oscillator start up time full swing Pierce 40MHz 3 tUPOSC 0 8 4 ms 5 D Clock Quality check time out tCQOUT 0 4...

Page 1238: ...e slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 5 Figure A 5 Jitter Definitions The relati...

Page 1239: ...re A 6 Maximum bus clock jitter approximation J N max 1 t max N N t nom 1 t min N N t nom J N j1 N j2 1 5 10 20 N J N Because of an order from the United States International Trade Commission BGA pack...

Page 1240: ...ime to lock tlock 214 150 256 fREF s 8 C Jitter fit parameter 13 3 fOSC 4MHz fBUS 50MHz equivalent fPLL 100MHz REFDIV 01 REFRQ 01 SYNDIV 18 VCOFRQ 11 POSTDIV 00 j1 1 2 9 C Jitter fit parameter 23 j2 0...

Page 1241: ...ll SPI output pins Avoid asymmetric load 50 pF Thresholds for delay measurement points 20 80 VDDX V SCK Output SCK Output MISO Input MOSI Output SS1 Output 1 9 5 6 MSB IN2 Bit MSB 1 1 LSB IN MSB OUT2...

Page 1242: ...IN2 Bit MSB 1 1 LSB IN Master MSB OUT2 Master LSB OUT Bit MSB 1 1 4 4 9 12 13 11 Port Data CPOL 0 CPOL 1 Port Data SS1 Output 2 12 13 3 1 If configured as output 2 LSBF 0 For LSBF 1 bit order is LSB b...

Page 1243: ...g time tlag 1 2 tsck 4 D Clock SCK high or low time twsck 1 2 tsck 5 D Data setup time inputs tsu 8 ns 6 D Data hold time inputs thi 8 ns 9 D Data valid after SCK edge tvsck 15 ns 10 D Data valid afte...

Page 1244: ...S Input 1 9 5 6 MSB IN Bit MSB 1 1 LSB IN Slave MSB Slave LSB OUT Bit MSB 1 1 11 4 4 2 7 CPOL 0 CPOL 1 3 13 NOTE Not defined 12 12 11 See 13 Note 8 10 See Note SCK Input SCK Input MOSI Input MISO Outp...

Page 1245: ...Data hold time inputs thi 8 ns 7 D Slave access time time to data active ta 20 ns 8 D Slave MISO disable time tdis 22 ns 9 D Data valid after SCK edge tvsck 28 0 5 tbus 1 1 0 5 tbus added due to inte...

Page 1246: ...st be off A 7 3 1 Normal Expanded Mode External Wait Feature Disabled Figure A 12 Example 1a Normal Expanded Mode Read Followed by Write CSx ADDRx RE DATAx ADDR1 ADDR2 Read DATA1 Write DATA2 WE EWAIT...

Page 1247: ...Sx tADRE D 4 D 13 ns 3 Pulse width RE PWRE D 28 D 58 ns 4 Address valid to WE fall tADWE D 4 D 15 ns 5 Pulse width WE PWWE D 18 D 38 ns 6 Read data setup time if ITHRS 0 tDSR D 19 D 38 ns Read data se...

Page 1248: ...mal Expanded Mode Stretched Read Access CSx ADDRx RE DATAx ADDR1 Read DATA1 WE EWAIT UDS LDS 3 6 7 1 8 2 ADDR2 12 13 Because of an order from the United States International Trade Commission BGA packa...

Page 1249: ...les Min Max Min Max Min Max Min Max Frequency of internal bus fi D C 50 0 D C 50 0 D C 25 0 D C 25 0 MHz Internal cycle time tcyc 20 20 20 20 ns Frequency of external bus fo D C 16 7 D C 12 5 D C 8 33...

Page 1250: ...a valid to WE fall tWDWE D 5 5 D 5 5 ns 10 Write data setup time tDSW D 63 93 D 123 163 ns 11 Write data hold time tDHW D 6 6 D 4 4 ns 12 Address to EWAIT fall tADWF D 0 16 0 36 D 0 20 0 ns 13 Address...

Page 1251: ...d data1 write data2 addr3 LSTRB ECLK2X 1 1 2 3 4 5 6 7 8 9 10 11 12 12 addr1 acc1 addr2 acc2 addr3 data0 addr1 addr2 addr3 iqstat0 iqstat1 ADDR ADDR 19 16 ADDR 22 20 15 0 ACC 2 0 IQSTAT 3 0 IVD 15 0 B...

Page 1252: ...lay time tAD 5 ns 5 D Address hold time tAH 0 ns 6 D IVDx delay time 2 2 Includes also ACCx IQSTATx tIVDD 4 5 ns 7 D IVDx hold time tIVDH 0 ns 8 D Read data setup time ITHRS 1 only tDSR 15 ns 9 D Read...

Page 1253: ...TRB ECLK2X 1 2 3 4 5 6 8 9 12 12 ADDR 19 16 Read DATA1 7 DATA0 ADDR1 ADDR1 ADDR2 ADDR1 IQSTAT0 ADDR1 ADDR2 ADDR 22 20 ADDR1 ACC1 ADDR1 000 ADDR2 15 0 IQSTAT1 ACC 2 0 IQSTAT 3 0 IVD 15 0 IVD1 Because o...

Page 1254: ...4 5 6 7 12 12 ADDR1 ADDR1 x ADDR2 ADDR1 IQSTAT0 ADDR1 ADDR2 ADDR1 ACC1 ADDR1 000 ADDR2 IQSTAT1 ADDR ADDR 19 16 ADDR 22 20 15 0 ACC 2 0 IQSTAT 3 0 IVD 15 0 Because of an order from the United States I...

Page 1255: ...8 32 48 52 68 72 ns 4 D Address delay time tAD refer to table Table A 32 refer to table Table A 32 refer to table Table A 32 ns 5 D Address hold time tAH ns 6 D IVD delay time 2 2 Includes also ACCx I...

Page 1256: ...ure only Symbol Min Max Unit D Frequency of internal bus fi D C 50 0 MHz 1 D Cycle time tcyc 20 ns 2 D TAGHI TAGLO setup time tTS 10 ns 3 D TAGHI TAGLO hold time tTH 0 ns ECLK R W DATAx TAGHI TAGLO 2...

Page 1257: ...tion provides the physical dimensions of the Sailfish packages Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here curr...

Page 1258: ...MILLIMETERS A 2 00 A1 0 40 0 60 A2 1 00 1 30 b 0 50 0 70 D 17 00 BSC E 17 00 BSC e 1 00 BSC S 0 50 BSC NOTES 1 2 3 4 5 ALL DIMENSIONS ARE IN MILLIMETERS INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y...

Page 1259: ...AA 0 09 0 16 0 0 7 11 13 1 2 NOTES 1 DIMENSIONS AND TOLERANCING PER ASME Y14 5M 1994 2 DIMENSIONS IN MILLIMETERS 3 DATUMS L M N TO BE DETERMINED AT THE SEATING PLANE DATUM T 4 DIMENSIONS S AND V TO B...

Page 1260: ...J1 VIEW Y J1 P G 108X 4X SECTION J1 J1 BASE ROTATED 90 COUNTERCLOCKWISE METAL J AA F D L M M 0 13 N T 1 2 3 C L L M 0 20 N T L N M T T 112X X X L M OR N R R NOTES 1 DIMENSIONING AND TOLERANCING PER AS...

Page 1261: ...L BE 0 08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT SECTION B B 61 60 DETAIL A L 41 40 80 A L D A S A B M 0 20 D S H 0 0...

Page 1262: ...ns between VSS1 VSS2 and VSS3 VSSPLL must be directly connected to VSS3 Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 and Q1 as small as possible Do not p...

Page 1263: ...8 LQFP144 only X7R tantalum 100 nF C9 VDD filter capacitor Ceramic X7R 220 nF C10 VDDA1 filter capacitor Ceramic X7R 100 nF C11 VDDX1 filter capacitor X7R tantalum 100 nF C12 VDDX5 filter capacitor MA...

Page 1264: ...ommended PCB Layout Loop Controlled Pierce Oscillator Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are...

Page 1265: ...ommended PCB Layout Loop Controlled Pierce Oscillator Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are...

Page 1266: ...mmended PCB Layout Loop Controlled Pierce Oscillator Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are...

Page 1267: ...144 LQFP 384K 16K 112 LQFP 80 QFP 9S12XET256 9S12XEA2561 1 The 9S12XEA128 256 are a special bondouts for access to extra ADC channels in 80QFP Available in 80QFP 256K 128K memory sizes only WARNING N...

Page 1268: ...112LQFP 4 6 3 1 8ch 0 4ch 2 162 91 80QFP 4 2 3 1 8ch 0 4ch 2 82 59 9S12XEG384 144LQFP 2 6 3 2 8ch 0 4ch 2 24 119 112LQFP 2 6 3 1 8ch 0 4ch 2 162 91 80QFP 2 2 3 1 8ch 0 4ch 2 82 59 9S12XES384 144LQFP n...

Page 1269: ...SPI1 and SPI2 Versions with 2 SPI modules will have SPI0 and SPI1 Versions with 1 SPI modules will have SPI0 Versions with 8 SCI modules will have SCI0 SCI1 SCI2 SCI3 SCI4 SCI5 SCI6 and SCI7 Versions...

Page 1270: ...0005 PORTD R PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 W 0x0006 DDRC R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W 0x0007 DDRD R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 W 0x0008 PORTE R PE7 PE6 PE...

Page 1271: ...3 PIX2 PIX1 PIX0 W 0x0016 RPAGE R RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 W 0x0017 EPAGE R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 W 0x0018 0x001B Miscellaneous Peripheral Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 1272: ...2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0 W 0x00281 1 This represents the contents if the Comparator A or C control register is blended into this address DBGXCTL COMPA C R 0 NDB TAG BRK RW R...

Page 1273: ...EFDIV4 REFDIV3 REFDIV2 REFDIV1 REFDIV0 W 0x0036 POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0037 CRGFLG R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W 0x0038 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0039 CLKSEL R...

Page 1274: ...W 0x0048 TCTL1 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x0049 TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x004A TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W 0x004B TCTL4 R EDG3B EDG3A EDG2B ED...

Page 1275: ...ACNT1 PACNT0 W 0x0064 PACN1 hi R PACNT7 15 PACNT6 14 PACNT5 13 PACNT4 12 PACNT3 11 PACNT2 10 PACNT1 9 PACNT0 8 W 0x0065 PACN0 lo R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0066 MCCT...

Page 1276: ...W 0x0077 MCCNT lo R MCCNT7 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT0 W 0x0078 TC0H hi R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 W 0x0079 TC0H lo R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W 0x007A TC1H h...

Page 1277: ...MPE7 CMPE6 CMPE5 CMPE4 CMPE3 CMPE2 CMPE1 CMPE0 W 0x008A ATD1STAT2H R CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 W 0x008B ATD1STATL R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 W 0x008C ATD1DIENH R IEN...

Page 1278: ...H R Bit15 14 13 12 11 10 9 Bit8 W 0x00A3 ATD1DR9L R Bit7 Bit6 0 0 0 0 0 0 W 0x00A4 ATD1DR10H R Bit15 14 13 12 11 10 9 Bit8 W 0x00A5 ATD1DR10L R Bit7 Bit6 0 0 0 0 0 0 W 0x00A6 ATD1DR11H R Bit15 14 13 1...

Page 1279: ...ATD1DR15L R Bit7 Bit6 0 0 0 0 0 0 W 0x0080 0x00AF Analog to Digital Converter 12 bit 16 Channels ATD1 Map Sheet 3 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Because of an order...

Page 1280: ...CI2SR2 register is set to zero R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x00B9 SCI2BDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x00BA SCI2CR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x00B8...

Page 1281: ...ible if the AMAP bit in the SCI3SR2 register is set to one R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x00C1 SCI3ACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE W 0x00C2 SCI3ACR22 R 0 0 0 0 0 BERRM1 BERRM0 BKDFE W...

Page 1282: ...RDRF IDLE OR NF FE PF W 0x00CD SCI0SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x00CE SCI0DRH R R8 T8 0 0 0 0 0 0 W 0x00CF SCI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0x00D0 0x00D7 A...

Page 1283: ...0x00DC SPI0DRH R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0x00DD SPI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0x00DE Reserved R 0 0 0 0 0 0 0 0 W 0x00DF Reserved R...

Page 1284: ...e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00F0 SPI1CR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W 0x00F1 SPI1CR2 R 0 XFRW 0 MODFEN BIDIROE 0 SPISWAI SPC0 W 0x00F2 SPI1BR R 0 SPPR2 SPPR1 SP...

Page 1285: ...FDIV3 FDIV2 FDIV1 FDIV0 W 0x0101 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0102 FCCOBIX R 0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W 0x0103 FECCRIX R 0 0 0 0 0 ECCRIX2 ECCRIX1 ECCRIX0 W 0x0104...

Page 1286: ...ECCR2 ECCR1 ECCR0 W 0x0110 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0111 Reserved R 0 0 0 0 0 0 0 0 W 0x0112 Reserved R 0 0 0 0 0 0 0 0 W 0x0113 Reserved R 0 0 0 0 0 0 0 0 W 0x0100 0x0113 NVM Contr...

Page 1287: ..._ADDR 18 11 W 0x011C MPUDESC21 R LOW_ADDR 10 3 W 0x011D MPUDESC31 R WP NEX 0 0 HIGH_ADDR 22 19 W 0x011E MPUDESC41 R HIGH_ADDR 18 11 W 0x011F MPUDESC51 R HIGH_ADDR 10 3 W 0x0120 0x012F Interrupt Module...

Page 1288: ...L 2 0 W 0x012D INT_CFDATA5 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012E INT_CFDATA6 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012F INT_CFDATA7 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x0120 0x012F Interrupt Module S12XINT Map conti...

Page 1289: ...RDRF IDLE OR NF FE PF W 0x0135 SCI4SR2 R AMAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x0136 SCI4DRH R R8 T8 0 0 0 0 0 0 W 0x0137 SCI4DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0x0138 0x013F A...

Page 1290: ...x0145 CAN0RIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0146 CAN0TFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0147 CAN0TIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0148 CAN0TARQ R 0 0 0 0 0 A...

Page 1291: ...ID R ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 Standard ID R ID2 ID1 ID0 RTR IDE 0 CANxRIDR1 W 0xXXX2 Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Standard ID R CANxRIDR2 W 0xXXX3 Extended ID R...

Page 1292: ...DB1 DB0 W 0xXX1C CANxTDLR R DLC3 DLC2 DLC1 DLC0 W 0xXX1D CANxTTBPR R PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 W 0xXX1E CANxTTSRH R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 W 0xXX1F CANxTTS...

Page 1293: ...x0189 CAN1TAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W 0x018A CAN1TBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x018B CAN1IDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 W 0x018C Reserved R 0 0 0 0 0 0 0 0 W 0x018D CAN1M...

Page 1294: ...ound Receive and Transmit Buffer Layout W 0x01C0 0x01FF MSCAN CAN2 Map Sheet 1 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x01C0 CAN2CTL0 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLP...

Page 1295: ...01D4 CAN2IDMR0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01D5 CAN2IDMR1 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01D6 CAN2IDMR2 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x01D7 CAN2IDMR3 R AM7 AM6 AM5 AM4 AM3 AM2...

Page 1296: ...x01FF CAN2TXFG R FOREGROUND TRANSMIT BUFFER See Detailed MSCAN Foreground Receive and Transmit Buffer Layout W 0x01C0 0x01FF MSCAN CAN2 Map Sheet 3 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit...

Page 1297: ...3TAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W 0x020A CAN3TBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x020B CAN3IDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 W 0x020C Reserved R 0 0 0 0 0 0 0 0 W 0x020D CAN3MISC R 0 0...

Page 1298: ...FFER See Detailed MSCAN Foreground Receive and Transmit Buffer Layout W 0x0240 0x027F Port Integration Module PIM Map 5 of 6 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0240 PTT R P...

Page 1299: ...x0255 PPSM R PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 W 0x0256 WOMM R WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 W 0x0257 MODRR R 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 W 0x025...

Page 1300: ...IEJ0 W 0x026f PIFJ R PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W 0x0270 PT0AD0 R PT0AD0 7 PT0AD0 6 PT0AD0 5 PT0AD0 4 PT0AD0 3 PT0AD0 2 PT0AD0 1 PT0AD0 0 W 0x0271 PT1AD0 R PT1AD0 7 PT1AD0 6 PT1AD...

Page 1301: ...Bit 1 Bit 0 0x0280 CAN4CTL0 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W 0x0281 CAN4CTL1 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W 0x0282 CAN4BTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1...

Page 1302: ...x0299 CAN4IDAR5 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x029A CAN4IDAR6 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x029B CAN4IDAR7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x029C CAN4IDMR4 R AM7 AM6 AM5 AM4 AM3 AM2...

Page 1303: ...PE6 CMPE5 CMPE4 CMPE3 CMPE2 CMPE1 CMPE0 W 0x02CA ATD0STAT2H R CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 CCF8 W 0x02CB ATD0STAT2L R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 W 0x02CC ATD0DIENH R IEN15 IEN...

Page 1304: ...10 9 Bit8 W 0x02E3 ATD0DR9L R Bit7 Bit6 0 0 0 0 0 0 W 0x02E4 ATD0DR10H R Bit15 14 13 12 11 10 9 Bit8 W 0x02E5 ATD0DR10L R Bit7 Bit6 0 0 0 0 0 0 W 0x02E6 ATD0DR11H R Bit15 14 13 12 11 10 9 Bit8 W 0x02E...

Page 1305: ...0 0 0 0 0 0 W 0x02C0 0x02EF Analog to Digital Converter 12 Bit 16 Channel ATD0 Map continued Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Because of an order from the United States In...

Page 1306: ...Reserved R 0 0 0 0 0 0 0 0 W 0x0300 0x0327 Pulse Width Modulator 8 Bit 8 Channel PWM Map Sheet 1 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0300 PWME R PWME7 PWME6 PWME5 PWME...

Page 1307: ...R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0316 PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0317 PWMPER3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0318 PWMPER4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0319 PWMPER5 R Bit 7 6 5 4 3 2 1 Bit 0 W...

Page 1308: ...1 Bit 0 0x0330 SCI6BDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0331 SCI6BDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0332 SCI6CR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0330 SCI6AS...

Page 1309: ...he SCI6SR2 register is set to zero 2 Those registers are accessible if the AMAP bit in the SCI6SR2 register is set to one 0x00330 0x0337 Asynchronous Serial Interface SCI6 Map continued Address Name B...

Page 1310: ...R R8 T8 0 0 0 0 0 0 W 0x033F SCI7DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0x00340 0x0367 Periodic Interrupt Timer PIT Map Sheet 1 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...

Page 1311: ...LD3 lo R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0356 PITCNT3 hi R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0357 PITCNT3 lo R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0...

Page 1312: ...LD11 PLD10 PLD9 PLD8 W 0x0365 PITLD7 lo R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0366 PITCNT7 hi R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0367 PITCNT7 lo R PCNT7 PCNT6 PCNT5 PC...

Page 1313: ...5 PTIL4 PTIL3 PTIL2 PTIL1 PTIL0 W 0x0372 DDRL R DDRL7 DDRL7 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0 W 0x0373 RDRL R RDRL7 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0 W 0x0374 PERL R PERL7 PERL6 PERL5 PERL4...

Page 1314: ...PTFRR4 PTFRR3 PTFRR2 PTFRR1 PTFRR0 W 0x0368 0x037F Port Integration Module PIM Map 6 of 6 continued Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Because of an order from the United Sta...

Page 1315: ...GIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 W 0x038D XGIF R XGIF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50 W 0x038E XGIF R XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 X...

Page 1316: ...W 0x03A1 Reserved R 0 0 0 0 0 0 0 0 W 0x03A2 XGR1 hi R XGR1 15 8 W 0x03A3 XGR1 lo R XGR1 7 0 W 0x03A4 XGR2 hi R XGR2 15 8 W 0x03A5 XGR2 lo R XGR2 7 0 W 0x03A6 XGR3 hi R XGR3 15 8 W 0x03A7 XGR3 lo R X...

Page 1317: ...BF Reserved R 0 0 0 0 0 0 0 0 W 0x0380 0x03BF XGATE Map Sheet 3 of 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Because of an order from the United States International Trade Commiss...

Page 1318: ...TTOV R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W 0x03D8 TCTL1 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x03D9 TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x03DA TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A ED...

Page 1319: ...EE TC7H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x03EF TC7L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x03F0 PACTL R 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W 0x03F1 PAFLG R...

Page 1320: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0400 0x07FF Reserved R 0 0 0 0 0 0 0 0 W Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers i...

Page 1321: ...the device For specific partnumbers to order please contact your local sales office The below figure illustrates the structure of a typical mask specific ordering number for the MC9S12XE Family devic...

Page 1322: ...emiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import...

Page 1323: ...nductor 1323 Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import...

Page 1324: ...emiconductor Because of an order from the United States International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import...

Page 1325: ...tes International Trade Commission BGA packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010...

Page 1326: ...scale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or...

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