Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
149
2.3.61
Port J Data Register (PTJ)
Address 0x0268
Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
W
Altern.
Function
TXCAN4
RXCAN4
—
—
—
—
TXD2
RXD2
SCL0
SDA0
SCL1
SDA1
—
—
—
—
(TXCAN0)
(RXCAN0)
CS2
CS0
—
CS1
—
CS3
Reset
0
0
0
0
0
0
0
0
Figure 2-59. Port J Data Register (PTJ)
Table 2-57. PTJ Register Field Descriptions
Field
Description
7-6
PTJ
Port J general purpose input/output data
—Data Register
Port J pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN4 and the routed CAN0, as well as with
SCL and SDA signals of IIC0, respectively.
The CAN4 function takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the
CAN4 module is enabled. The IIC0 function takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as
open drain outputs. The routed CAN0 function takes precedence over the general purpose I/O function if the routed
CAN0 module is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5-4
PTJ
Port J general purpose input/output data
—Data Register
This pin is associated with the SCL and SDA signals of IIC1, and with chip select outputs CS2 and CS0, respectivley.
The IIC1 function takes precedence over the chip select and general purpose I/O function if the IIC1 is enabled. The
chip selects take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1
outputs are configured as open drain outputs. Refer to IIC section for details.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTJ
Port J general purpose input/output data
—Data Register
This pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTJ
Port J general purpose input/output data
—Data Register
This pin is associated with the chip select output signal CS2
.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
