Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
160
Freescale Semiconductor
2.3.78
Port AD1 Data Register 1 (PT1AD1)
2.3.79
Port AD1 Data Direction Register 0 (DDR0AD1)
Address 0x0279
Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PT1AD17
PT1AD16
PT1AD15
PT1AD14
PT1AD13
PT1AD12
PT1AD11
PT1AD10
W
Altern.
Function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Reset
0
0
0
0
0
0
0
0
Figure 2-76. Port AD1 Data Register 1 (PT1AD1)
Table 2-74. PT1AD1 Register Field Descriptions
Field
Description
7-0
PT1AD1
Port AD1 general purpose input/output data
—Data Register
This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Address 0x027A
Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDR0AD17
DDR0AD16
DDR0AD15
DDR0AD14
DDR0AD13
DDR0AD12
DDR0AD11
DDR0AD10
W
Reset
0
0
0
0
0
0
0
0
Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)
Table 2-75. DDR0AD1 Register Field Descriptions
Field
Description
7-0
DDR0AD1
Port AD1 data direction
—
This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
