Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
161
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR0AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
2.3.80
Port AD1 Data Direction Register 1 (DDR1AD1)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR1AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
Address 0x027B
Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDR1AD17
DDR1AD16
DDR1AD15
DDR1AD14
DDR1AD13
DDR1AD12
DDR1AD11
DDR1AD10
W
Reset
0
0
0
0
0
0
0
0
Figure 2-78. Port AD1 Data Direction Register 1 (DDR1AD1)
Table 2-76. DDR1AD1 Register Field Descriptions
Field
Description
7-0
DDR1AD1
Port AD1 data direction
—
This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
