Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
170
Freescale Semiconductor
2.3.94
Port L Input Register (PTIL)
2.3.95
Port L Data Direction Register (DDRL)
Address 0x0371
Access: User read
(1)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
7
6
5
4
3
2
1
0
R
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
W
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-92. Port L Input Register (PTIL)
Table 2-89. PTIL Register Field Descriptions
Field
Description
7-0
PTIL
Port L input data
—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Address 0x0372
Access: User read/write
(1)
1. Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDRL7
DDRL6
DDRL5
DDRL4
DDRL3
DDRL2
DDRL1
DDRL0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-93. Port L Data Direction Register (DDRL)
Table 2-90. DDRL Register Field Descriptions
Field
Description
7-0
DDRL
Port L data direction
—
This register controls the data direction of pins 7 through 0.This register configures each Port L pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction.
Refer to SPI section for details
.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
