Chapter 4 Memory Protection Unit (S12XMPUV1)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
239
ranges with the NEX bit set adjacent to memory used for program code. The best way to do this would be
to leave some fill-bytes between the memory ranges in this case, i.e. do not set the upper memory boundary
to the address of the last op-code but to a following address which is at least two words (four bytes) away.
4.4.2
Interrupts
This section describes all interrupts originated by the MPU module.
4.4.2.1
Description of Interrupt Operation
The MPU module generates one interrupt request. It cannot be masked locally in the MPU module and is
meant to be used as the source of a non-maskable hardware interrupt request for the S12X CPU
4.4.2.2
CPU Access Error Interrupt
An S12X CPU access error interrupt request is generated if the MPU module has detected an illegal
memory access originating from the S12X CPU. This is a non-maskable hardware interrupt. Due to the
non-maskable nature of this interrupt, the de-assertion of this interrupt request is coupled to the S12X CPU
interrupt vector fetch instead of the local access error flag (AEF). This means leaving the access error flag
(AEF) in the MPUFLG register set will not cause the same interrupt to be serviced again after leaving the
interrupt service routine with “RTI”. Instead, the interrupt request will be asserted again only when the
next illegal S12X CPU access is detected.
4.5
Initialization/Application Information
4.5.1
Initialization
After reset the MPU module is in an unconfigured state, with all eight protection descriptors covering the
whole memory map. The master bits are all set for descriptor “0” and cleared for all other descriptors. The
S12XCPU in supervisor state can access everything because the SVSEN bit in the MPUSEL register is
cleared by a system reset. After system reset every master has full access to the memory map because of
descriptor “0”.
In order to use the MPU module to protect memory ranges from undesired accesses, software needs to:
•
Initialize the protection descriptors.
•
Make sure there are meaningful interrupt service routines defined for the Access Violation
interrupts because these are non-maskable (See S12XINT chapter for details).
•
Initialize peripherals and other masters for use (i.e. set-up XGATE, Master3 if applicable).
•
Enable the MPU protection for the S12X CPU in supervisor state, if desired.
•
Switch the S12X CPU to user state, if desired.
Table 4-15. Interrupt vectors
Interrupt Source
CCR Mask Local Enable
S12X CPU access error interrupt (AEF)
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