Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
245
5.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the
XEBI
.
5.3.1
Module Memory Map
The registers associated with the XEBI block are shown in
5.3.2
Register Descriptions
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
NOTE
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
5.3.2.1
External Bus Interface Control Register 0 (EBICTL0)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes, the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0E
EBICTL0
R
ITHRS
0
HDBE
ASIZ4
ASIZ3
ASIZ2
ASIZ1
ASIZ0
W
0x0F
EBICTL1
R
0
EXSTR12
EXSTR11
EXSTR10
0
EXSTR02
EXSTR01
EXSTR00
W
= Unimplemented or Reserved
Figure 5-2. XEBI Register Summary
Module Base +0x000E (PRR)
7
6
5
4
3
2
1
0
R
ITHRS
0
HDBE
ASIZ4
ASIZ3
ASIZ2
ASIZ1
ASIZ0
W
Reset
0
0
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 5-3. External Bus Interface Control Register 0 (EBICTL0)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
