Chapter 7 Background Debug Module (S12XBDMV2)
MC9S12XE-Family Reference Manual , Rev. 1.19
284
Freescale Semiconductor
7.3.2.2
BDM CCR LOW Holding Register (BDMCCRL)
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR
L
register
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
L
register in this CPU mode. Out of reset in all other modes the
BDMCCRL register is read zero.
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
7.3.2.3
BDM CCR HIGH Holding Register (BDMCCRH)
Figure 7-5. BDM CCR HIGH Holding Register (BDMCCRH)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
Register Global Address 0x7FFF06
7
6
5
4
3
2
1
0
R
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
W
Reset
Special Single-Chip Mode
1
1
0
0
1
0
0
0
All Other Modes
0
0
0
0
0
0
0
0
Register Global Address 0x7FFF07
7
6
5
4
3
2
1
0
R
0
0
0
0
0
CCR10
CCR9
CCR8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
