Chapter 7 Background Debug Module (S12XBDMV2)
MC9S12XE-Family Reference Manual , Rev. 1.19
292
Freescale Semiconductor
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
Figure 7-8. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated.
shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
Target Senses Bit
10 Cycles
Synchronization
Uncertainty
BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time
Earliest
Start of
Next Bit
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
