Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual , Rev. 1.19
312
Freescale Semiconductor
8.3.2.4
Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 8-12. TRANGE Trace Range Encoding
TRANGE
Tracing Range
00
Trace from all addresses (No filter)
01
Trace only in address range from $00000 to Comparator D
10
Trace only in address range from Comparator C to $7FFFFF
11
Trace only in range from Comparator C to Comparator D
Table 8-13. TRCMOD Trace Mode Bit Encoding
TRCMOD
Description
00
Normal
01
Loop1
10
Detail
11
Pure PC
Table 8-14. TALIGN Trace Alignment Encoding
TALIGN
Description
00
Trigger at end of stored data
01
Trigger before storing data
10
Trace buffer entries before and after trigger
11
Reserved
Address: 0x0023
7
6
5
4
3
2
1
0
R
0
0
0
0
CDCM
ABCM
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-6. Debug Control Register2 (DBGC2)
Table 8-15. DBGC2 Field Descriptions
Field
Description
3–2
CDCM[1:0]
C and D Comparator Match Control
— These bits determine the C and D comparator match mapping as
described in
1–0
ABCM[1:0]
A and B Comparator Match Control
— These bits determine the A and B comparator match mapping as
described in
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
