Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
321
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
8.3.2.8.2
Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See
for visible register encoding.
Write: If DBG not armed. See
for visible register encoding.
1
SRC
Determines mapping of comparator to CPU12X or XGATE
0 The comparator is mapped to CPU12X buses
1 The comparator is mapped to XGATE address and data buses
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 8-31. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
0
Write
1
0
1
No match
1
1
0
No match
1
1
1
Read
Address: 0x0029
7
6
5
4
3
2
1
0
R
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Address High Register (DBGXAH)
Table 8-32. DBGXAH Field Descriptions
Field
Description
6–0
Bit[22:16]
Comparator Address High Compare Bits
— The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is
ignored for XGATE compares.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Table 8-30. DBGXCTL Field Descriptions (continued)
Field
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
