Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
360
Freescale Semiconductor
Read: Anytime
Write: In Debug Mode
1
10.3.1.3
XGATE Channel Priority Level (XGCHPL)
The XGATE Channel Priority Level Register (
) shows the priority level of the current thread.
In debug mode this register can be used to select a priority level when launching a thread (see
Section 10.6.1, “Debug Features”
).
Read: Anytime
Write: In Debug Mode
10.3.1.4
XGATE Initial Stack Pointer Select Register (XGISPSEL)
The XGATE Initial Stack Pointer Select Register (
) determines the register which is mapped
to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting
Module Base +0x0002
7
6
5
4
3
2
1
0
R
0
XGCHID[6:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-4. XGATE Channel ID Register (XGCHID)
Table 10-3. XGCHID Field Descriptions
Field
Description
6–0
XGCHID[6:0]
Request Identifier
— ID of the currently active channel
1. Refer to
Section 10.6.1, “Debug Features
Module Base +0x0003
7
6
5
4
3
2
1
0
R
0
0
0
0
0
XGCHPL[2:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. XGATE Channel Priority Level Register (XGCHPL)
Table 10-4. XGCHPL Field Descriptions
Field
Description
2-0
XGCHPL[2:0]
Priority Level
— Priority level of the currently active channel
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
