Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
380
Freescale Semiconductor
10.8
Instruction Set
10.8.1
Addressing Modes
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all
operations must have one of the eight general purpose registers R0 … R7 as their source as well their
destination.
All word accesses must work with a word aligned address, that is A[0] = 0!
10.8.1.1
Naming Conventions
RD
Destination register, allowed range is R0–R7
RD.L
Low byte of the destination register, bits [7:0]
RD.H
High byte of the destination register, bits [15:8]
RS, RS1, RS2
Source register, allowed range is R0–R7
RS.L, RS1.L, RS2.L
Low byte of the source register, bits [7:0]
RS.H, RS1.H, RS2.H
High byte of the source register, bits[15:8]
RB
Base register for indexed addressing modes, allowed
range is R0–R7
RI
Offset register for indexed addressing modes with
register offset, allowed range is R0–R7
RI+
Offset register for indexed addressing modes with
register offset and post-increment,
Allowed range is R0–R7 (R0+ is equivalent to R0)
–RI
Offset register for indexed addressing modes with
register offset and pre-decrement,
Allowed range is R0–R7 (–R0 is equivalent to R0)
NOTE
Even though register R1 is intended to be used as a pointer to the data
segment, it may be used as a general purpose data register as well.
Selecting R0 as destination register will discard the result of the instruction.
Only the condition code register will be updated
10.8.1.2
Inherent Addressing Mode (INH)
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE
registers.
Examples:
BRK
RTS
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
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currently
are
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available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
