Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
388
Freescale Semiconductor
Operation
RS1 + RS2
⇒
RD
RD
+
IMM16
⇒
RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #IMM16[15:8])
Performs a 16 bit addition and stores the result in the destination register RD.
NOTE
When using immediate addressing mode (ADD RD, #IMM16), the V-flag
and the C-Flag of the first instruction (ADDL RD, #IMM16[7:0]) are not
considered by the second instruction (ADDH RD, #IMM16[15:8]).
⇒
Don’t rely on the V-Flag if RD + IMM16[7:0]
≥
2
15
.
⇒
Don’t rely on the C-Flag if RD + IMM16[7:0]
≥
2
16
.
CCR Effects
Code and CPU Cycles
ADD
Add without Carry
ADD
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
new
| RS1[15] & RS2[15] & RD[15]
new
Refer to ADDH instruction for #IMM16 operations.
C:
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
new
| RS2[15] & RD[15]
new
Refer to ADDH instruction for #IMM16 operations.
Source Form
Address
Mode
Machine Code
Cycles
ADD RD, RS1, RS2
TRI
0
0
0
1
1
RD
RS1
RS2
1
0
P
ADD RD, #IMM16
IMM8
1
1
1
0
0
RD
IMM16[7:0]
P
IMM8
1
1
1
0
1
RD
IMM16[15:8]
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
