Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
421
Operation
RS.L – IMM8
⇒
NONE, only condition code flags get updated
Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register
RS.L using binary subtraction and updates the condition code register accordingly.
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
Code and CPU Cycles
CMPL
Compare Immediate 8 bit Constant
(Low Byte)
CMPL
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 7 of the result is set; cleared otherwise.
Z:
Set if the 8 bit result is $00; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RS[7] & IMM8[7] & result[7] | RS[7] & IMM8[7] & result[7]
C:
Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise.
RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7]
Source Form
Address
Mode
Machine Code
Cycles
CMPL RS, #IMM8
IMM8
1
1
0
1
0
RS
IMM8
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
