Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
423
Operation
RS1 – RS2 - C
⇒
NONE (translates to SBC R0, RS1, RS2)
Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary
subtraction and discards the result.
CCR Effects
Code and CPU Cycles
CPC
Compare with Carry
CPC
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
C:
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
Source Form
Address
Mode
Machine Code
Cycles
CPC RS1, RS2
TRI
0
0
0
1
1
0
0
0
RS1
RS2
0
1
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
