Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
436
Freescale Semiconductor
Operation
–RS
⇒
RD (translates to SUB RD, R0, RS)
–RD
⇒
RD (translates to SUB RD, R0, RD)
Performs a two’s complement on a general purpose register.
CCR Effects
Code and CPU Cycles
NEG
Two’s Complement
NEG
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & RD[15]
new
C:
Set if there is a carry from the bit 15 of the result; cleared otherwise
RS[15] | RD[15]
new
Source Form
Address
Mode
Machine Code
Cycles
NEG RD, RS
TRI
0
0
0
1
1
RD
0
0
0
RS
0
0
P
NEG RD
TRI
0
0
0
1
1
RD
0
0
0
RD
0
0
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
