Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
438
Freescale Semiconductor
Operation
RS1
|
RS2
⇒
RD
RD
|
IMM16
⇒
RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8]
Performs a bit wise logical OR between two 16 bit values and stores the result in the destination
register RD.
NOTE
When using immediate addressing mode (OR RD, #IMM16), the Z-flag of
the first instruction (ORL RD, #IMM16[7:0]) is not considered by the
second instruction (ORH RD, #IMM16[15:8]).
⇒
Don’t rely on the Z-Flag.
CCR Effects
Code and CPU Cycles
OR
Logical OR
OR
N
Z
V
C
∆
∆
0
—
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000; cleared otherwise.
Refer to ORH instruction for #IMM16 operations.
V:
0; cleared.
C:
Not affected.
Source Form
Address
Mode
Machine Code
Cycles
OR RD, RS1, RS2
TRI
0
0
0
1
0
RD
RS1
RS2
1
0
P
OR RD, #IMM16
IMM8
1
0
1
0
0
RD
IMM16[7:0]
P
IMM8
1
0
1
0
1
RD
IMM16[15:8]
P
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
