Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
450
Freescale Semiconductor
Operation
RS
⇒
M[RB, #OFFS5
]
RS
⇒
M[RB, RI
]
RS
⇒
M[RB, RI];
RI+2
⇒
RI;
RI–2
⇒
RI;
RS
⇒
M[RB, RI]
1
Stores the content of register RS to memory.
CCR Effects
Code and CPU Cycles
STW
Store Word to Memory
STW
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS
⇒
M[RB, RS–2]; RS–2
⇒
RS
N
Z
V
C
—
—
—
—
N:
Not affected.
Z:
Not affected.
V:
Not affected.
C:
Not affected.
Source Form
Address
Mode
Machine Code
Cycles
STW RS, (RB, #OFFS5)
IDO5
0
1
0
1
1
RS
RB
OFFS5
PW
STW RS, (RB, RI)
IDR
0
1
1
1
1
RS
RB
RI
0
0
PW
STW RS, (RB, RI+)
IDR+
0
1
1
1
1
RS
RB
RI
0
1
PW
STW RS, (RB, -RI)
-IDR
0
1
1
1
1
RS
RB
RI
1
0
PW
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
