MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
467
Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1)
11.1
Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1
Features
The main features of this block are:
•
Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
•
System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
•
Computer Operating Properly (COP) watchdog timer with time-out clear window.
•
System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
Table 11-1. Revision History
Revision
Number
Revision
Date
Sections
Affected
Description of Changes
V01.00
26 Oct. 2005
Initial release
V01.01
02 Nov 2006
Table “Examples of IPLL Divider settings”: corrected $32 to $31
V01.02
4 Mar. 2008
11.4.1.4/11-487
11.4.3.3/11-491
Corrected details
V01.03
1 Sep. 2008
added 100MHz example for PLL
V01.04
20 Nov. 2008
S12XECRG Flags Register: corrected address to Module Base + 0x0003
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
