Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
488
Freescale Semiconductor
The Sequence for clock quality check is shown in
Figure 11-18. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset
1
handling the clock quality checker
continues
to
check the OSCCLK signal.
NOTE
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (f
SCM
) and an active VREG
during Pseudo Stop Mode.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
CHECK WINDOW
OSC OK
?
SCM
ACTIVE?
SWITCH TO OSCCLK
EXIT SCM
CLOCK OK
NUM = 50
NUM > 0
?
NUM = NUM-1
YES
NO
YES
SCME = 1
?
NO
ENTER SCM
SCM
ACTIVE?
YES
CLOCK MONITOR RESET
NO
YES
NO
NUM = 0
YES
NO
POR
EXIT FULL STOP
CM FAIL
LVR
SCME=1 &
?
FSTWKP=1
YES
NO
?
FSTWKP = 0
NO
NUM = 0
ENTER SCM
YES
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
