Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
540
Freescale Semiconductor
14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1 (TSCR1)”
.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in
Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”
).
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
W
Reset
0
0
0
0
0
0
0
0
Figure 14-17. Main Timer Interrupt Flag 1 (TFLG1)
Table 14-16. TFLG1 Field Descriptions
Field
Description
7:0
C[7:0]F
Input Capture/Output Compare Channel “x” Flag
— A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
Table 14-15. Prescaler Selection (continued)
PR2
PR1
PR0
Prescale Factor
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
