Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
546
Freescale Semiconductor
14.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1 (TSCR1)”
.
All bits reset to zero.
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
Section 14.3.2.6, “Timer System Control Register 1 (TSCR1)”
).
Table 14-20. Clock Selection
CLK1
CLK0
Clock Source
0
0
Use timer prescaler clock as timer counter clock
0
1
Use PACLK as input to timer counter clock
1
0
Use PACLK/256 as timer counter clock frequency
1
1
Use PACLK/65536 as timer counter clock frequency
Module Base + 0x0021
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PAOVF
PAIF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-36. Pulse Accumulator A Flag Register (PAFLG)
Table 14-21. PAFLG Field Descriptions
Field
Description
1
PAOVF
Pulse Accumulator A Overflow Flag
— Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on PT3.
0
PAIF
Pulse Accumulator Input edge Flag
— Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the PT7 input pin triggers PAIF.
Because
of
an
order
from
the
United
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International
Trade
Commission,
BGA-packaged
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