Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
553
14.3.2.24 Input Control System Control Register (ICSYS)
Read: Anytime
Write: Once in normal modes
All bits reset to zero.
Table 14-29. ICOVW Field Descriptions
Field
Description
7:0
NOVW[7:0]
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
or latch occurs.
1 The related capture register or holding register cannot be written by an event unless they are empty (see
Section 14.4.1.1, “IC Channels”
). This will prevent the captured value being overwritten until it is read or
latched in the holding register.
Module Base + 0x002B
7
6
5
4
3
2
1
0
R
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
W
Reset
0
0
0
0
0
0
0
0
Figure 14-46. Input Control System Register (ICSYS)
Table 14-30. ICSYS Field Descriptions
Field
Description
7:4
SHxy
Share Input action of Input Capture Channels x and y
0 Normal operation
1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge
detector is used to be active on the channel ‘y’.
3
TFMOD
Timer Flag Setting Mode
— Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers
are emptied, an input capture event will first update the related input capture register with the main timer
contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF
interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on PTx.
0 The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin
occurs.
1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 are set only when a latch
on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD = 0.
2
PACMX
8-Bit Pulse Accumulators Maximum Count
0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,
it will be incremented to 0x0000.
1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value
0x00FF indicates a count of 255 or more.
Because
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an
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International
Trade
Commission,
BGA-packaged
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