Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual , Rev. 1.19
Freescale Semiconductor
595
15.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
15.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
15.4.1.10 Ten-bit Address
A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules
apply to the first address byte.
The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the
address is 10-bit address.Generally, there are two cases of 10-bit address.See the Fig.1-14 and 1-15.
In the figure 1-15,the first two bytes are the similar to figure1-14.After the repeated START(Sr),the first
slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter.
15.4.1.11 General Call Address
To broadcast using a general call, a device must first generate the general call address($00), then after
receiving acknowledge, it must transmit data.
In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast
and receives data until the GCEN is disabled or the master device releases the bus or generates a new
Table 15-11. Definition of Bits in the First Byte
SLAVE
ADDRESS
R/W BIT
DESCRIPTION
0000000
0
General call address
0000010
x
Reserved for different bus format
0000011
x
Reserved for future purposes
11111XX
x
Reserved for future purposes
11110XX
x
10-bit slave addressing
S
Slave Add1st 7bits
11110+ADR10+ADR9
R/W
0
A1
Slave Add 2nd byte
ADR[8:1]
A2
Data
A3
Figure 15-13. A master-transmitter addresses a slave-receiver with a 10-bit address
S
Slave Add1st 7bits
11110+ADR10+ADR9
R/W
0
A1
Slave Add 2nd byte
ADR[8:1]
A2
Sr
Slave Add 1st 7bits
11110+ADR10+ADR9
R/W
1
A3
Data
A4
Figure 15-14. A master-receiver addresses a slave-transmitter with a 10-bit address
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