Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MC9S12XE-Family Reference Manual , Rev. 1.19
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Freescale Semiconductor
transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the
address match.
In order to distinguish whether the address match is the normal address match or the general call address
match, IBDR should be read after the address byte has been received. If the data is $00, the match is
general call address match. The meaning of the general call address is always specified in the first data byte
and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte.
When one byte transfer is done, the received data can be read from IBDR. The user can control the
procedure by enabling or disabling GCEN.
15.4.2
Operation in Run Mode
This is the basic mode of operation.
15.4.3
Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
15.4.4
Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
15.5
Resets
The reset state of each individual bit is listed in
Section 15.3, “Memory Map and Register Definition
,”
which details the registers and their bit-fields.
15.6
Interrupts
IICV3 uses only one interrupt vector.
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
1. Arbitration lost condition (IBAL bit set)
Table 15-12. Interrupt Summary
Interrupt
Offset
Vector
Priority
Source
Description
IIC
Interrupt
—
—
—
IBAL, TCF, IAAS
bits in IBSR
register
When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
lost, transfer complete or address detect
conditions
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