Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
624
Freescale Semiconductor
Read: Anytime
Write: Anytime; write of ‘1’ clears flag; write of ‘0’ ignored
16.3.2.15 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
BOHOLD
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-17. MSCAN Miscellaneous Register (CANMISC)
Table 16-20. CANMISC Register Field Descriptions
Field
Description
0
BOHOLD
Bus-off State Hold Until User Request
— If BORM is set in
Section 16.3.2.2, “MSCAN Control Register 1
this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the
recovery from bus-off. Refer to
Section 16.5.2, “Bus-Off Recovery
,” for details.
0 Module is not bus-off or recovery has been requested by user in bus-off state
1 Module is bus-off and holds this state until user request
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-18. MSCAN Receive Error Counter (CANRXERR)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
