Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
638
Freescale Semiconductor
16.3.3.4
Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number.
The MSCAN implements the following internal prioritization mechanisms:
•
All transmission buffers with a cleared TXEx flag participate in the prioritization immediately
before the SOF (start of frame) is sent.
•
The transmission buffer with the lowest local priority field wins the prioritization.
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
Read: Anytime when TXEx flag is set (see
Section 16.3.2.7, “MSCAN Transmitter Flag Register
”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register (CANTBSEL)
”).
Write: Anytime when TXEx flag is set (see
Section 16.3.2.7, “MSCAN Transmitter Flag Register
”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register (CANTBSEL)
”).
16.3.3.5
Time Stamp Register (TSRH–TSRL)
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0 (CANCTL0)
”). In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Module Base + 0xXXXD
7
6
5
4
3
2
1
0
R
PRIO7
PRIO6
PRIO5
PRIO4
PRIO3
PRIO2
PRIO1
PRIO0
W
Reset:
0
0
0
0
0
0
0
0
Figure 16-36. Transmit Buffer Priority Register (TBPR)
Module Base + 0xXXXE
7
6
5
4
3
2
1
0
R
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
W
Reset:
x
x
x
x
x
x
x
x
Figure 16-37. Time Stamp Register — High Byte (TSRH)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
