Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
673
Figure 17-28. PIT Trigger and Flag Signal Timing
17.4.2
Interrupt Interface
Each time-out event can be used to trigger an interrupt service request. For each timer channel, an
individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE
is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out
flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit.
NOTE
Be careful when resetting the PITE, PINTE or PITCE bits in case of pending
PIT interrupt requests, to avoid spurious interrupt requests.
17.4.3
Hardware Trigger
The PIT module contains eight hardware trigger signal lines PITTRIG[7:0], one for each timer channel.
These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion
(please refer to the device overview for the mapping of PITTRIG[7:0] signals to peripheral modules).
Whenever a timer channel time-out is reached, the corresponding PTF flag is set and the corresponding
trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of
two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register
values PITLD = 0x0001 and PITMTLD = 0x0002 the flag setting, trigger timing and a restart with force
load is shown in
.
Bus Clock
0
2
1
0
8-Bit Micro
2
1
0
2
1
0
2
1
2
1
0
PITCNT Register
0001
0000
00
0001
0000
8-Bit Force Load
2
1
0
2
1
0
PTF Flag
1
PITTRIG
16-Bit Force Load
0001
0000
0001
2
Time-Out Period
Time-Out Period
After Restart
Timer Counter
Note 1. The PTF flag clearing depends on the software
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