Chapter 21 Serial Peripheral Interface (S12SPIV5)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
773
Figure 21-9. Reception with SPIF serviced in Time
Figure 21-10. Reception with SPIF serviced too late
21.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set,
the four associated SPI port pins are dedicated to the SPI function as:
•
Slave select (SS)
•
Serial clock (SCK)
•
Master out/slave in (MOSI)
•
Master in/slave out (MISO)
Receive Shift Register
SPIF
SPI Data Register
Data A
Data B
Data A
Data A Received
Data B Received
Data C
Data C
SPIF Serviced
Data C Received
Data B
= Unspecified
= Reception in progress
Receive Shift Register
SPIF
SPI Data Register
Data A
Data B
Data A
Data A Received
Data B Received
Data C
Data C
SPIF Serviced
Data C Received
Data B Lost
= Unspecified
= Reception in progress
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
