Chapter 1 Device Overview MC9S12XE-Family
MC9S12XE-Family Reference Manual , Rev. 1.19
88
Freescale Semiconductor
1.12
Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used. For this device XCLKS is mapped to PE7.
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
•
Power on reset or low-voltage reset
•
Clock monitor reset
•
Any reset while in self-clock mode or full stop mode
The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.
Figure 1-10. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
Figure 1-11. Full Swing Pierce Oscillator Connections (XCLKS = 0)
Figure 1-12. External Clock Connections (XCLKS = 0)
MCU
EXTAL
XTAL
V
SSPLL
Crystal or
Ceramic Resonator
C
2
C
1
MCU
EXTAL
XTAL
R
S
R
B
V
SSPLL
Crystal or
Ceramic Resonator
C
2
C
1
R
B
=1M
Ω ;
R
S
specified by crystal vendor
MCU
EXTAL
XTAL
CMOS-Compatible
External Oscillator
Not Connected
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
