Chapter 2 Port Integration Module (S12XEP100PIMV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
92
Freescale Semiconductor
E
PE[7]
XCLKS
I
External clock selection input during RESET
Mode
dependent
ECLKX2
I
Free-running clock output at Core Clock rate (ECLK x 2)
GPIO
I/O General-purpose I/O
PE[6]
MODB
I
MODB input during RESET
TAGHI
I
Instruction tagging low pin
Configurable for reduced input threshold
GPIO
I/O General-purpose I/O
PE[5]
MODA
I
MODA input during RESET
RE
O
Read enable signal
TAGLO
I
Instruction tagging low pin
Configurable for reduced input threshold
GPIO
I/O General-purpose I/O
PE[4]
ECLK
O
Free-running clock output at the Bus Clock rate or programmable
divided in normal modes
GPIO
I/O General-purpose I/O
PE[3]
EROMCTL
I
EROMON bit control input during RESET
LSTRB
O
Low strobe bar output
LDS
O
Lower data strobe
GPIO
I/O General-purpose I/O
PE[2]
RW
O
Read/write output for external bus
WE
O
Write enable signal
GPIO
I/O General-purpose I/O
PE[1]
IRQ
I
Maskable level- or falling edge-sensitive interrupt input
GPI
I
General-purpose input
PE[0]
XIRQ
I
Non-maskable level-sensitive interrupt input
GPI
I
General-purpose input
K
PK[7]
ROMCTL
I
ROMON bit control input during RESET
Mode
dependent
EWAIT
I
External Wait signal
Configurable for reduced input threshold
GPIO
I/O General-purpose I/O
PK[6:4]
ADDR[22:20]
mux
ACC[2:0]
O
Extended external bus address output
(multiplexed with access master output)
GPIO
I/O General-purpose I/O
PK[3:0]
ADDR[19:16]
mux
IQSTAT[3:0]
O
Extended external bus address output
(multiplexed with instruction pipe status bits)
GPIO
I/O General-purpose I/O
Port
Pin Name
Pin Function
& Priority
(1)
I/O
Description
Pin Function
after Reset
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
