Chapter 3 Memory Mapping Control (S12XMMCV4)
MC9S12XE-Family Reference Manual , Rev. 1.19
194
Freescale Semiconductor
shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Table 3-6. MMCCTL0 Field Descriptions
Field
Description
7–6
CS3E[1:0]
Chip Select 3 Enables
— These bits enable the external chip select CS3 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 3 is disabled
01,10,11 Chip select 3 is enabled
5–4
CS2E[1:0]
Chip Select 2 Enables
— These bits enable the external chip select CS2 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Chip select 2 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 2 is disabled
01,10,11 Chip select 2 is enabled
3–2
CS1E[1:0]
Chip Select 1 Enables
— These bits enable the external chip select CS1 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Chip select 1 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 1 is disabled
01,10,11 Chip select 1 is enabled
1–0
CS0E[1:0]
Chip Select 0 Enables
— These bits enable the external chip select CS0 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in
Chip select 0 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 0 is disabled
01,10,11 Chip select 0 is enabled
Table 3-7. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
0x00_0800
0x0F_FFFF minus RAMSIZE
(1)
1. External RPAGE accesses in (NX, EX)
CS2
(2)
2. When ROMHM is set (see ROMHM in
) the CS2 is asserted in the space occupied by this on-
chip memory block.
0x14_0000
0x1F_FFFF
CS1
0x20_0000
0x3F_FFFF
CS0
(3)
3. When the internal NVM is enabled (see ROMON in
Section 3.3.2.5, “MMC Control Register (MMCCTL1)
the CS0 is not asserted in the space occupied by this on-chip memory block.
0x40_0000
0x7F_FFFF minus FLASHSIZE
(4)
4. External PPAGE accesses in (NX, EX)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
