Chapter 3 Memory Mapping Control (S12XMMCV4)
MC9S12XE-Family Reference Manual Rev. 1.19
Freescale Semiconductor
197
3.3.2.3
Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Figure 3-7. GPAGE Address Mapping
Example 3-1. This example demonstrates usage of the GPAGE register
LDX
#0x5000
;Set GPAGE offset to the value of 0x5000
MOVB
#0x14, GPAGE
;Initialize GPAGE register with the value of 0x14
GLDAA
X
;Load Accu A from the global address 0x14_5000
Address: 0x0010
7
6
5
4
3
2
1
0
R
0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-6. Global Page Index Register (GPAGE)
Table 3-9. GPAGE Field Descriptions
Field
Description
6–0
GP[6:0]
Global Page Index Bits 6–0
— These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Bit16
Bit 0
Bit15
Bit22
CPU Address [15:0]
GPAGE Register [6:0]
Global Address [22:0]
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages
