Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.19
378
Freescale Semiconductor
•
Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core
registers will be updated accordingly.
•
Write accesses to the XGCHID register and the XGCHPL register
XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the
XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is
shown in
. Once a thread has been initiated it’s code can be either single stepped or it
can be executed by leaving debug mode.
NOTE
Even though zero is not a valid interrupt priority level of the S12X_INT
module, a thread of priority level 0 can be initiated in debug mode. The
XGATE handles requests of priority level 0 in the same way as it handles
requests of priority levels 1 to 3.
NOTE
All channels 1 to 127 can be initiated by writing to the XGCHID register,
even if they are not assigned to any peripheral module.
NOTE
In Debug Mode the XGATE will ignore all requests from peripheral
modules.
10.6.1.0.1
Entering Debug Mode
Debug mode can be entered in four ways:
1. Setting XGDBG to "1"
Table 10-22. Initiating and Terminating Threads in Debug Mode
Register Content
Single Cycle Write
Access to...
Action
XGCHID
XGCHPL
XGCHID
XGCHPL
0
0
1..127
-
(1)
1. 8 bit write access to XGCHID
Set new XGCHID
Set XGCHPL to 0x01
Initiate new thread
0
0
1..127
0..7
Set new XGCHID
Set new XGCHPL
Initiate new thread
1..127
0..3
1..127
4..7
Interrupt current thread
Set new XGCHID
Set new XGCHPL
Initiate new thread
1..127
0..7
0
0..7
Terminate current thread.
Resume interrupted thread or become idle if
no interrupted thread is pending
-
All other combinations
No action
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